Single step appears to work.
[riscv-isa-sim.git] / riscv / insns / dret.h
1 require_privilege(PRV_M);
2 set_pc_and_serialize(STATE.dpc);
3 p->set_privilege(STATE.dcsr.prv);
4
5 /* We're not in Debug Mode anymore. */
6 STATE.dcsr.cause = 0;
7
8 if (STATE.dcsr.step)
9 STATE.single_step = STATE.STEP_STEPPING;