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Support debug system bus access.
[riscv-isa-sim.git]
/
riscv
/
insns
/
ecall.h
1
switch
(
STATE
.
prv
)
2
{
3
case
PRV_U
:
throw
trap_user_ecall
();
4
case
PRV_S
:
throw
trap_supervisor_ecall
();
5
case
PRV_M
:
throw
trap_machine_ecall
();
6
default
:
abort
();
7
}