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Support debug system bus access.
[riscv-isa-sim.git] / riscv / insns / fcvt_q_d.h
1 require_extension('Q');
2 require_fp;
3 softfloat_roundingMode = RM;
4 WRITE_FRD(f64_to_f128(f64(FRS1)));
5 set_fp_exceptions;
Simple-V augmented version of spike