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[sim,xcc] change cond. mov inst format, add implementation
[riscv-isa-sim.git]
/
riscv
/
insns
/
fmovz.h
1
require_vector
;
2
if
(~
RS1
&
0x1
)
FRD
=
FRS2
;
projects / riscv-isa-sim.git / blob