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FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
[riscv-isa-sim.git] / riscv / insns / fmv_x_w.h
1 require_extension('F');
2 require_fp;
3 WRITE_RD(sext32(FRS1.v));
Simple-V augmented version of spike