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[riscv-isa-sim.git] / riscv / insns / fnmadd_q.h

require_extension('Q');
require_fp;
softfloat_roundingMode = RM;
WRITE_FRD(f128_mulAdd(f128_negate(f128(FRS1)), f128(FRS2), f128_negate(f128(FRS3))));
set_fp_exceptions;