riscv/insns/mfpcr.h

   1 require_supervisor;
   2
   3 reg_t val;
   4
   5 switch(insn.rtype.rs2)
   6 {
   7   case 0:
   8     val = sr;
   9     break;
  10   case 1:
  11     val = epc;
  12     break;
  13   case 2:
  14     val = badvaddr;
  15     break;
  16   case 3:
  17     val = evec;
  18     break;
  19   case 4:
  20     val = count;
  21     break;
  22   case 5:
  23     val = compare;
  24     break;
  25   case 6:
  26     val = cause;
  27     break;
  28
  29   case 8:
  30     val = MEMSIZE >> PGSHIFT;
  31     break;
  32
  33   case 9:
  34     val = mmu.get_ptbr();
  35     break;
  36
  37   case 10:
  38     val = id;
  39     break;
  40
  41   case 11:
  42     val = vecbanks;
  43     break;
  44
  45   case 12:
  46     val = sim->num_cores();
  47     break;
  48
  49   case 17:
  50     fromhost = val = sim->get_fromhost();
  51     break;
  52
  53   case 24:
  54     val = pcr_k0;
  55     break;
  56   case 25:
  57     val = pcr_k1;
  58     break;
  59
  60   default:
  61     val = -1;
  62 }
  63
  64 RD = sext_xprlen(val);