riscv/insns/mfpcr.h

   1 require_supervisor;
   2 require64;
   3
   4 switch(insn.rtype.rb)
   5 {
   6   case 0:
   7     RA = sr;
   8     break;
   9   case 1:
  10     RA = epc;
  11     break;
  12   case 2:
  13     RA = badvaddr;
  14     break;
  15   case 3:
  16     RA = ebase;
  17     break;
  18
  19   case 8:
  20     RA = MEMSIZE >> 12;
  21     break;
  22
  23   case 17:
  24     RA = sim->get_fromhost();
  25     break;
  26
  27   default:
  28     RA = -1;
  29 }