riscv/insns/mfpcr.h

   1 require_supervisor;
   2
   3 reg_t val;
   4
   5 switch(insn.rtype.rs2)
   6 {
   7   case 0:
   8     val = sr;
   9     break;
  10   case 1:
  11     val = epc;
  12     break;
  13   case 2:
  14     val = badvaddr;
  15     break;
  16   case 3:
  17     val = evec;
  18     break;
  19   case 4:
  20     val = count;
  21     break;
  22   case 5:
  23     val = compare;
  24     break;
  25   case 6:
  26     val = cause;
  27     break;
  28   case 7:
  29     cause &= ~(1 << (IPI_IRQ+CAUSE_IP_SHIFT));
  30     break;
  31
  32   case 8:
  33     val = MEMSIZE >> PGSHIFT;
  34     break;
  35
  36   case 9:
  37     val = mmu.get_ptbr();
  38     break;
  39
  40   case 10:
  41     val = id;
  42     break;
  43
  44   case 11:
  45     val = vecbanks;
  46     break;
  47
  48   case 12:
  49     val = sim->num_cores();
  50     break;
  51
  52   case 17:
  53     fromhost = val = sim->get_fromhost();
  54     break;
  55
  56   case 24:
  57     val = pcr_k0;
  58     break;
  59   case 25:
  60     val = pcr_k1;
  61     break;
  62
  63   default:
  64     val = -1;
  65 }
  66
  67 RD = sext_xprlen(val);