[sim] add while to interactive_until
[riscv-isa-sim.git] / riscv / insns / mtpcr.h
1 require_supervisor;
2
3 reg_t val = gprlen == 64 ? RA : sext32(RA);
4
5 switch(insn.rtype.rb)
6 {
7 case 0:
8 set_sr(val);
9 break;
10 case 1:
11 epc = val;
12 break;
13 case 3:
14 ebase = val & ~0xFFF;
15 break;
16
17 case 16:
18 tohost = val;
19 sim->set_tohost(tohost);
20 break;
21
22 case 24:
23 pcr_k0 = val;
24 break;
25 case 25:
26 pcr_k1 = val;
27 break;
28 }