riscv/insns/mtpcr.h

   1 require_supervisor;
   2
   3 switch(insn.rtype.rs2)
   4 {
   5   case 0:
   6     set_sr(RS1);
   7     break;
   8   case 1:
   9     epc = RS1;
  10     break;
  11   case 3:
  12     evec = RS1;
  13     break;
  14   case 4:
  15     count = RS1;
  16     break;
  17   case 5:
  18     interrupts_pending &= ~(1 << TIMER_IRQ);
  19     compare = RS1;
  20     break;
  21   case 7:
  22     mmu.set_ptbr(RS1);
  23     break;
  24
  25   case 8:
  26     sim.send_ipi(RS1);
  27     break;
  28   case 9:
  29     interrupts_pending &= ~(1 << IPI_IRQ);
  30     break;
  31
  32   case 12:
  33     pcr_k0 = RS1;
  34     break;
  35   case 13:
  36     pcr_k1 = RS1;
  37     break;
  38
  39   case 16:
  40     sim.set_tohost(RS1);
  41     break;
  42
  43   case 18:
  44     vecbanks = RS1 & 0xff;
  45     vecbanks_count = __builtin_popcountll(vecbanks);
  46     break;
  47 }