reimplement div[u][w]/rem[u][w]
[riscv-isa-sim.git] / riscv / insns / rem.h
1 sreg_t lhs = sext_xprlen(RS1);
2 sreg_t rhs = sext_xprlen(RS2);
3 if(rhs == 0)
4 RD = lhs;
5 else if(lhs == INT64_MIN && rhs == -1)
6 RD = 0;
7 else
8 RD = sext_xprlen(lhs % rhs);