Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / srli.h

if(xpr64)
  WRITE_RD(RS1 >> SHAMT);
else
{
  if(SHAMT & 0x20)
    throw trap_illegal_instruction();
  WRITE_RD(sext32((uint32_t)RS1 >> SHAMT));
}