5 #include "debug_module.h"
6 #include "debug_defines.h"
20 #define DTMCONTROL_VERSION 0xf
21 #define DTMCONTROL_ABITS (0x3f << 4)
22 #define DTMCONTROL_DBUSSTAT (3<<10)
23 #define DTMCONTROL_IDLE (7<<12)
24 #define DTMCONTROL_DBUSRESET (1<<16)
27 #define DBUS_DATA (0xffffffffL<<2)
28 #define DBUS_ADDRESS ((1L<<(abits+34)) - (1L<<34))
30 #define DBUS_OP_STATUS_SUCCESS 0
31 #define DBUS_OP_STATUS_RESERVED 1
32 #define DBUS_OP_STATUS_FAILED 2
33 #define DBUS_OP_STATUS_BUSY 3
36 #define DBUS_OP_READ 1
37 #define DBUS_OP_READ_WRITE 2
38 #define DBUS_OP_RESERVED 3
40 jtag_dtm_t::jtag_dtm_t(debug_module_t
*dm
) :
42 dtmcontrol((abits
<< DTM_DTMCONTROL_ABITS_OFFSET
) | 1),
43 dbus(DBUS_OP_STATUS_FAILED
<< DTM_DBUS_OP_OFFSET
),
44 state(TEST_LOGIC_RESET
)
48 void jtag_dtm_t::reset() {
49 state
= TEST_LOGIC_RESET
;
52 void jtag_dtm_t::set_pins(bool tck
, bool tms
, bool tdi
) {
53 const jtag_state_t next
[16][2] = {
54 /* TEST_LOGIC_RESET */ { RUN_TEST_IDLE
, TEST_LOGIC_RESET
},
55 /* RUN_TEST_IDLE */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
},
56 /* SELECT_DR_SCAN */ { CAPTURE_DR
, SELECT_IR_SCAN
},
57 /* CAPTURE_DR */ { SHIFT_DR
, EXIT1_DR
},
58 /* SHIFT_DR */ { SHIFT_DR
, EXIT1_DR
},
59 /* EXIT1_DR */ { PAUSE_DR
, UPDATE_DR
},
60 /* PAUSE_DR */ { PAUSE_DR
, EXIT2_DR
},
61 /* EXIT2_DR */ { SHIFT_DR
, UPDATE_DR
},
62 /* UPDATE_DR */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
},
63 /* SELECT_IR_SCAN */ { CAPTURE_IR
, TEST_LOGIC_RESET
},
64 /* CAPTURE_IR */ { SHIFT_IR
, EXIT1_IR
},
65 /* SHIFT_IR */ { SHIFT_IR
, EXIT1_IR
},
66 /* EXIT1_IR */ { PAUSE_IR
, UPDATE_IR
},
67 /* PAUSE_IR */ { PAUSE_IR
, EXIT2_IR
},
68 /* EXIT2_IR */ { SHIFT_IR
, UPDATE_IR
},
69 /* UPDATE_IR */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
}
73 // Positive clock edge.
78 dr
|= (uint64_t) _tdi
<< (dr_length
-1);
82 ir
|= _tdi
<< (ir_length
-1);
87 state
= next
[state
][_tms
];
89 case TEST_LOGIC_RESET
:
114 D(fprintf(stderr, "state=%2d, tdi=%d, tdo=%d, tms=%d, tck=%d, ir=0x%02x, "
116 state, _tdi, _tdo, _tms, _tck, ir, dr));
124 void jtag_dtm_t::capture_dr()
137 dr_length
= abits
+ 34;
140 D(fprintf(stderr
, "Unsupported IR: 0x%x\n", ir
));
143 D(fprintf(stderr
, "Capture DR; IR=0x%x, DR=0x%lx (%d bits)\n",
147 void jtag_dtm_t::update_dr()
149 D(fprintf(stderr
, "Update DR; IR=0x%x, DR=0x%lx (%d bits)\n",
154 unsigned op
= get_field(dr
, DBUS_OP
);
155 uint32_t data
= get_field(dr
, DBUS_DATA
);
156 unsigned address
= get_field(dr
, DBUS_ADDRESS
);
161 if (op
== DBUS_OP_READ
|| op
== DBUS_OP_READ_WRITE
) {
163 if (dm
->dmi_read(address
, &value
)) {
164 dbus
= set_field(dbus
, DBUS_DATA
, value
);
169 if (success
&& op
== DBUS_OP_READ_WRITE
) {
170 success
= dm
->dmi_write(address
, data
);
174 dbus
= set_field(dbus
, DBUS_OP
, DBUS_OP_STATUS_SUCCESS
);
176 dbus
= set_field(dbus
, DBUS_OP
, DBUS_OP_STATUS_FAILED
);
178 D(fprintf(stderr
, "dbus=0x%lx\n", dbus
));