27 static const unsigned idcode_ir
= 1;
28 static const unsigned idcode_dr
= 0xdeadbeef;
29 static const unsigned dtmcontrol_ir
= 0x10;
37 state(TEST_LOGIC_RESET
) {}
40 state
= TEST_LOGIC_RESET
;
43 void set_pins(bool tck
, bool tms
, bool tdi
);
45 bool tdo() const { return _tdo
; }
48 bool _tck
, _tms
, _tdi
, _tdo
;
50 const unsigned ir_length
= 5;
61 const jtag_state_t next
[16][2] = {
62 /* TEST_LOGIC_RESET */ { RUN_TEST_IDLE
, TEST_LOGIC_RESET
},
63 /* RUN_TEST_IDLE */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
},
64 /* SELECT_DR_SCAN */ { CAPTURE_DR
, SELECT_IR_SCAN
},
65 /* CAPTURE_DR */ { SHIFT_DR
, EXIT1_DR
},
66 /* SHIFT_DR */ { SHIFT_DR
, EXIT1_DR
},
67 /* EXIT1_DR */ { PAUSE_DR
, UPDATE_DR
},
68 /* PAUSE_DR */ { PAUSE_DR
, EXIT2_DR
},
69 /* EXIT2_DR */ { SHIFT_DR
, UPDATE_DR
},
70 /* UPDATE_DR */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
},
71 /* SELECT_IR_SCAN */ { CAPTURE_IR
, TEST_LOGIC_RESET
},
72 /* CAPTURE_IR */ { SHIFT_IR
, EXIT1_IR
},
73 /* SHIFT_IR */ { SHIFT_IR
, EXIT1_IR
},
74 /* EXIT1_IR */ { PAUSE_IR
, UPDATE_IR
},
75 /* PAUSE_IR */ { PAUSE_IR
, EXIT2_IR
},
76 /* EXIT2_IR */ { SHIFT_IR
, UPDATE_IR
},
77 /* UPDATE_IR */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
}