Update README.md for freg info
[riscv-isa-sim.git] / riscv / mulhi.h
1 #ifndef _RISCV_MULHI_H
2 #define _RISCV_MULHI_H
3
4 #include <cstdint>
5
6 inline uint64_t mulhu(uint64_t a, uint64_t b)
7 {
8 uint64_t t;
9 uint32_t y1, y2, y3;
10 uint64_t a0 = (uint32_t)a, a1 = a >> 32;
11 uint64_t b0 = (uint32_t)b, b1 = b >> 32;
12
13 t = a1*b0 + ((a0*b0) >> 32);
14 y1 = t;
15 y2 = t >> 32;
16
17 t = a0*b1 + y1;
18 y1 = t;
19
20 t = a1*b1 + y2 + (t >> 32);
21 y2 = t;
22 y3 = t >> 32;
23
24 return ((uint64_t)y3 << 32) | y2;
25 }
26
27 inline int64_t mulh(int64_t a, int64_t b)
28 {
29 int negate = (a < 0) != (b < 0);
30 uint64_t res = mulhu(a < 0 ? -a : a, b < 0 ? -b : b);
31 return negate ? ~res + (a * b == 0) : res;
32 }
33
34 inline int64_t mulhsu(int64_t a, uint64_t b)
35 {
36 int negate = a < 0;
37 uint64_t res = mulhu(a < 0 ? -a : a, b);
38 return negate ? ~res + (a * b == 0) : res;
39 }
40
41 #endif