riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include "devices.h"
   8 #include <string>
   9 #include <vector>
  10 #include <map>
  11
  12 class processor_t;
  13 class mmu_t;
  14 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  15 class sim_t;
  16 class trap_t;
  17 class extension_t;
  18 class disassembler_t;
  19
  20 struct insn_desc_t
  21 {
  22   insn_bits_t match;
  23   insn_bits_t mask;
  24   insn_func_t rv32;
  25   insn_func_t rv64;
  26 };
  27
  28 struct commit_log_reg_t
  29 {
  30   reg_t addr;
  31   reg_t data;
  32 };
  33
  34 typedef struct
  35 {
  36   uint8_t prv;
  37   bool step;
  38   bool debugint;
  39   bool ebreakm;
  40   bool ebreakh;
  41   bool ebreaks;
  42   bool ebreaku;
  43   bool halt;
  44   uint8_t cause;
  45 } dcsr_t;
  46
  47 // architectural state of a RISC-V hart
  48 struct state_t
  49 {
  50   void reset();
  51
  52   reg_t pc;
  53   regfile_t<reg_t, NXPR, true> XPR;
  54   regfile_t<freg_t, NFPR, false> FPR;
  55
  56   // control and status registers
  57   reg_t prv;
  58   reg_t mstatus;
  59   reg_t mepc;
  60   reg_t mbadaddr;
  61   reg_t mscratch;
  62   reg_t mtvec;
  63   reg_t mcause;
  64   reg_t minstret;
  65   reg_t mie;
  66   reg_t mip;
  67   reg_t medeleg;
  68   reg_t mideleg;
  69   reg_t mucounteren;
  70   reg_t mscounteren;
  71   reg_t sepc;
  72   reg_t sbadaddr;
  73   reg_t sscratch;
  74   reg_t stvec;
  75   reg_t sptbr;
  76   reg_t scause;
  77   reg_t dpc;
  78   reg_t dscratch;
  79   dcsr_t dcsr;
  80
  81   uint32_t fflags;
  82   uint32_t frm;
  83   bool serialized; // whether timer CSRs are in a well-defined state
  84
  85   reg_t load_reservation;
  86
  87 #ifdef RISCV_ENABLE_COMMITLOG
  88   commit_log_reg_t log_reg_write;
  89   reg_t last_inst_priv;
  90 #endif
  91 };
  92
  93 typedef enum {
  94       HR_NONE,
  95       HR_STEPPED,       // A single step was completed
  96       HR_SWBP,          // sbreak was executed
  97       HR_INTERRUPT,     // Execution interrupted by debugger
  98       HR_CMDLINE,       // Command line requested that the processor start halted
  99       HR_ATTACHED       // Halted because a debugger attached
 100 } halt_reason_t;
 101
 102 // this class represents one processor in a RISC-V machine.
 103 class processor_t : public abstract_device_t
 104 {
 105 public:
 106   processor_t(const char* isa, sim_t* sim, uint32_t id);
 107   ~processor_t();
 108
 109   void set_debug(bool value);
 110   void set_histogram(bool value);
 111   void reset(bool value);
 112   void step(size_t n); // run for n cycles
 113   bool running() { return run; }
 114   void set_csr(int which, reg_t val);
 115   void raise_interrupt(reg_t which);
 116   reg_t get_csr(int which);
 117   mmu_t* get_mmu() { return mmu; }
 118   state_t* get_state() { return &state; }
 119   extension_t* get_extension() { return ext; }
 120   bool supports_extension(unsigned char ext) {
 121     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
 122     return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
 123   }
 124   void set_privilege(reg_t);
 125   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
 126   void update_histogram(reg_t pc);
 127
 128   void register_insn(insn_desc_t);
 129   void register_extension(extension_t*);
 130
 131   // MMIO slave interface
 132   bool load(reg_t addr, size_t len, uint8_t* bytes);
 133   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 134
 135 private:
 136   sim_t* sim;
 137   mmu_t* mmu; // main memory is always accessed via the mmu
 138   extension_t* ext;
 139   disassembler_t* disassembler;
 140   state_t state;
 141   uint32_t id;
 142   unsigned max_xlen;
 143   unsigned xlen;
 144   reg_t isa;
 145   std::string isa_string;
 146   bool run; // !reset
 147   // When true, display disassembly of each instruction that's executed.
 148   bool debug;
 149   bool histogram_enabled;
 150
 151   std::vector<insn_desc_t> instructions;
 152   std::map<reg_t,uint64_t> pc_histogram;
 153
 154   static const size_t OPCODE_CACHE_SIZE = 8191;
 155   insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
 156
 157   void check_timer();
 158   void take_interrupt(); // take a trap if any interrupts are pending
 159   void take_trap(trap_t& t, reg_t epc); // take an exception
 160   void disasm(insn_t insn); // disassemble and print an instruction
 161
 162   void enter_debug_mode(uint8_t cause);
 163
 164   friend class sim_t;
 165   friend class mmu_t;
 166   friend class rtc_t;
 167   friend class extension_t;
 168   friend class gdbserver_t;
 169
 170   void parse_isa_string(const char* isa);
 171   void build_opcode_map();
 172   void register_base_instructions();
 173   insn_func_t decode_insn(insn_t insn);
 174 };
 175
 176 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 177
 178 #define REGISTER_INSN(proc, name, match, mask) \
 179   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 180   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 181   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 182
 183 #endif