1 // See LICENSE for license details.
2 #ifndef _RISCV_PROCESSOR_H
3 #define _RISCV_PROCESSOR_H
14 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
28 struct commit_log_reg_t
47 // architectural state of a RISC-V hart
53 regfile_t
<reg_t
, NXPR
, true> XPR
;
54 regfile_t
<freg_t
, NFPR
, false> FPR
;
56 // control and status registers
83 bool serialized
; // whether timer CSRs are in a well-defined state
85 reg_t load_reservation
;
87 #ifdef RISCV_ENABLE_COMMITLOG
88 commit_log_reg_t log_reg_write
;
95 HR_STEPPED
, // A single step was completed
96 HR_SWBP
, // sbreak was executed
97 HR_INTERRUPT
, // Execution interrupted by debugger
98 HR_CMDLINE
, // Command line requested that the processor start halted
99 HR_ATTACHED
// Halted because a debugger attached
102 // this class represents one processor in a RISC-V machine.
103 class processor_t
: public abstract_device_t
106 processor_t(const char* isa
, sim_t
* sim
, uint32_t id
);
109 void set_debug(bool value
);
110 void set_halted(bool value
, halt_reason_t reason
);
111 void set_single_step(bool value
);
112 void set_histogram(bool value
);
113 void reset(bool value
);
114 void step(size_t n
); // run for n cycles
115 bool running() { return run
; }
116 void set_csr(int which
, reg_t val
);
117 void raise_interrupt(reg_t which
);
118 reg_t
get_csr(int which
);
119 mmu_t
* get_mmu() { return mmu
; }
120 state_t
* get_state() { return &state
; }
121 extension_t
* get_extension() { return ext
; }
122 bool supports_extension(unsigned char ext
) {
123 if (ext
>= 'a' && ext
<= 'z') ext
+= 'A' - 'a';
124 return ext
>= 'A' && ext
<= 'Z' && ((isa
>> (ext
- 'A')) & 1);
126 void set_privilege(reg_t
);
127 void yield_load_reservation() { state
.load_reservation
= (reg_t
)-1; }
128 void update_histogram(reg_t pc
);
130 void register_insn(insn_desc_t
);
131 void register_extension(extension_t
*);
133 // MMIO slave interface
134 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
135 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
139 mmu_t
* mmu
; // main memory is always accessed via the mmu
141 disassembler_t
* disassembler
;
147 std::string isa_string
;
149 // When true, display disassembly of each instruction that's executed.
151 // TODO: Should this just be rolled into `run`?
152 bool halted
; // When true, no instructions are executed.
153 halt_reason_t halt_reason
; // Why is halted true?
154 // When true, execute exactly one instruction (even if halted is true), then
155 // set halted to true and single_step to false.
157 bool histogram_enabled
;
159 std::vector
<insn_desc_t
> instructions
;
160 std::map
<reg_t
,uint64_t> pc_histogram
;
162 static const size_t OPCODE_CACHE_SIZE
= 8191;
163 insn_desc_t opcode_cache
[OPCODE_CACHE_SIZE
];
166 void take_interrupt(); // take a trap if any interrupts are pending
167 void take_trap(trap_t
& t
, reg_t epc
); // take an exception
168 void disasm(insn_t insn
); // disassemble and print an instruction
173 friend class extension_t
;
174 friend class gdbserver_t
;
176 void parse_isa_string(const char* isa
);
177 void build_opcode_map();
178 void register_base_instructions();
179 insn_func_t
decode_insn(insn_t insn
);
182 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
);
184 #define REGISTER_INSN(proc, name, match, mask) \
185 extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
186 extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
187 proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});