riscv/processor.h

   1 #ifndef _RISCV_PROCESSOR_H
   2 #define _RISCV_PROCESSOR_H
   3
   4 #include "decode.h"
   5 #include <cstring>
   6 #include "trap.h"
   7 #include "mmu.h"
   8
   9 class sim_t;
  10
  11 class processor_t
  12 {
  13 public:
  14   processor_t(sim_t* _sim, char* _mem, size_t _memsz);
  15   void init(uint32_t _id);
  16   void step(size_t n, bool noisy);
  17
  18 private:
  19   sim_t* sim;
  20
  21   // architected state
  22   reg_t R[NGPR];
  23   freg_t FR[NFPR];
  24
  25   // privileged control registers
  26   reg_t pc;
  27   reg_t epc;
  28   reg_t badvaddr;
  29   reg_t ebase;
  30   reg_t pcr_k0;
  31   reg_t pcr_k1;
  32   uint32_t id;
  33   uint32_t sr;
  34   uint32_t count;
  35   uint32_t compare;
  36   uint32_t interrupts_pending;
  37
  38   // unprivileged control registers
  39   uint32_t tid;
  40   uint32_t fsr;
  41
  42   // 32-bit or 64-bit mode (redundant with sr)
  43   int gprlen;
  44
  45   // shared memory
  46   mmu_t mmu;
  47
  48   // counters
  49   reg_t counters[32];
  50
  51   // functions
  52   void set_sr(uint32_t val);
  53   void set_fsr(uint32_t val);
  54   void take_trap(trap_t t, bool noisy);
  55   void disasm(insn_t insn, reg_t pc);
  56
  57   friend class sim_t;
  58 };
  59
  60 #endif