riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include "devices.h"
   8 #include <string>
   9 #include <vector>
  10 #include <map>
  11
  12 class processor_t;
  13 class mmu_t;
  14 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  15 class sim_t;
  16 class trap_t;
  17 class extension_t;
  18 class disassembler_t;
  19
  20 struct insn_desc_t
  21 {
  22   insn_bits_t match;
  23   insn_bits_t mask;
  24   insn_func_t rv32;
  25   insn_func_t rv64;
  26 };
  27
  28 struct commit_log_reg_t
  29 {
  30   reg_t addr;
  31   reg_t data;
  32 };
  33
  34 // architectural state of a RISC-V hart
  35 struct state_t
  36 {
  37   void reset();
  38
  39   reg_t pc;
  40   regfile_t<reg_t, NXPR, true> XPR;
  41   regfile_t<freg_t, NFPR, false> FPR;
  42
  43   // control and status registers
  44   reg_t prv;
  45   reg_t mstatus;
  46   reg_t mepc;
  47   reg_t mbadaddr;
  48   reg_t mscratch;
  49   reg_t mtvec;
  50   reg_t mcause;
  51   reg_t minstret;
  52   reg_t mie;
  53   reg_t mip;
  54   reg_t medeleg;
  55   reg_t mideleg;
  56   reg_t mucounteren;
  57   reg_t mscounteren;
  58   reg_t sepc;
  59   reg_t sbadaddr;
  60   reg_t sscratch;
  61   reg_t stvec;
  62   reg_t sptbr;
  63   reg_t scause;
  64   uint32_t fflags;
  65   uint32_t frm;
  66   bool serialized; // whether timer CSRs are in a well-defined state
  67
  68   reg_t load_reservation;
  69
  70 #ifdef RISCV_ENABLE_COMMITLOG
  71   commit_log_reg_t log_reg_write;
  72   reg_t last_inst_priv;
  73 #endif
  74 };
  75
  76 // this class represents one processor in a RISC-V machine.
  77 class processor_t : public abstract_device_t
  78 {
  79 public:
  80   processor_t(const char* isa, sim_t* sim, uint32_t id);
  81   ~processor_t();
  82
  83   void set_debug(bool value);
  84   void set_halted(bool value);
  85   void set_single_step(bool value);
  86   void set_histogram(bool value);
  87   void reset(bool value);
  88   void step(size_t n); // run for n cycles
  89   bool running() { return run; }
  90   void set_csr(int which, reg_t val);
  91   void raise_interrupt(reg_t which);
  92   reg_t get_csr(int which);
  93   mmu_t* get_mmu() { return mmu; }
  94   state_t* get_state() { return &state; }
  95   extension_t* get_extension() { return ext; }
  96   bool supports_extension(unsigned char ext) {
  97     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
  98     return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
  99   }
 100   void set_privilege(reg_t);
 101   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
 102   void update_histogram(reg_t pc);
 103
 104   void register_insn(insn_desc_t);
 105   void register_extension(extension_t*);
 106
 107   // MMIO slave interface
 108   bool load(reg_t addr, size_t len, uint8_t* bytes);
 109   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 110
 111 private:
 112   sim_t* sim;
 113   mmu_t* mmu; // main memory is always accessed via the mmu
 114   extension_t* ext;
 115   disassembler_t* disassembler;
 116   state_t state;
 117   uint32_t id;
 118   unsigned max_xlen;
 119   unsigned xlen;
 120   reg_t isa;
 121   std::string isa_string;
 122   bool run; // !reset
 123   // When true, display disassembly of each instruction that's executed.
 124   bool debug;
 125   // TODO: Should this just be rolled into `run`?
 126   bool halted;  // When true, no instructions are executed.
 127   // When true, execute exactly one instruction (even if halted is true), then
 128   // set halted to true and single_step to false.
 129   bool single_step;
 130   bool histogram_enabled;
 131
 132   std::vector<insn_desc_t> instructions;
 133   std::map<reg_t,uint64_t> pc_histogram;
 134
 135   static const size_t OPCODE_CACHE_SIZE = 8191;
 136   insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
 137
 138   void check_timer();
 139   void take_interrupt(); // take a trap if any interrupts are pending
 140   void take_trap(trap_t& t, reg_t epc); // take an exception
 141   void disasm(insn_t insn); // disassemble and print an instruction
 142
 143   friend class sim_t;
 144   friend class mmu_t;
 145   friend class rtc_t;
 146   friend class extension_t;
 147   friend class gdbserver_t;
 148
 149   void parse_isa_string(const char* isa);
 150   void build_opcode_map();
 151   void register_base_instructions();
 152   insn_func_t decode_insn(insn_t insn);
 153 };
 154
 155 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 156
 157 #define REGISTER_INSN(proc, name, match, mask) \
 158   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 159   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 160   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 161
 162 #endif