1 #ifndef _RISCV_PROCESSOR_H
2 #define _RISCV_PROCESSOR_H
12 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
15 // this class represents one processor in a RISC-V machine.
19 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
);
22 void step(size_t n
, bool noisy
); // run for n cycles
23 void deliver_ipi(); // register an interprocessor interrupt
27 mmu_t
& mmu
; // main memory is always accessed via the mmu
29 // user-visible architected state
38 // privileged control registers
46 uint32_t sr
; // only modify the status register using set_sr()
50 // # of bits in an XPR (32 or 64). (redundant with sr)
53 // is this processor running? (deliver_ipi() sets this)
57 void reset(); // resets architected state; halts processor if it was running
58 void take_interrupt(); // take a trap if any interrupts are pending
59 void set_sr(uint32_t val
); // set the status register
60 void set_fsr(uint32_t val
); // set the floating-point status register
61 void take_trap(trap_t t
, bool noisy
); // take an exception
62 void disasm(insn_t insn
, reg_t pc
); // disassemble and print an instruction
66 void setvl(int vlapp
);
69 uint32_t vecbanks_count
;
78 processor_t
* uts
[MAX_UTS
];
80 // this constructor is used for each of the uts
81 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
, uint32_t _utidx
);