riscv/processor.h

   1 #ifndef _RISCV_PROCESSOR_H
   2 #define _RISCV_PROCESSOR_H
   3
   4 #include "decode.h"
   5 #include <cstring>
   6 #include "trap.h"
   7 #include "mmu.h"
   8
   9 class sim_t;
  10
  11 class processor_t
  12 {
  13 public:
  14   processor_t(sim_t* _sim, char* _mem, size_t _memsz);
  15   void init(uint32_t _id);
  16   void step(size_t n, bool noisy);
  17
  18 private:
  19   sim_t* sim;
  20
  21   // architected state
  22   reg_t R[NGPR];
  23   freg_t FR[NFPR];
  24
  25   // privileged control registers
  26   reg_t pc;
  27   reg_t epc;
  28   reg_t badvaddr;
  29   reg_t cause;
  30   reg_t evec;
  31   reg_t tohost;
  32   reg_t fromhost;
  33   reg_t pcr_k0;
  34   reg_t pcr_k1;
  35   uint32_t id;
  36   uint32_t sr;
  37   uint32_t count;
  38   uint32_t compare;
  39   uint32_t interrupts_pending;
  40
  41   // unprivileged control registers
  42   uint32_t fsr;
  43
  44   // 32-bit or 64-bit mode (redundant with sr)
  45   int gprlen;
  46
  47   // shared memory
  48   mmu_t mmu;
  49
  50   // counters
  51   reg_t counters[32];
  52
  53   // functions
  54   void set_sr(uint32_t val);
  55   void set_fsr(uint32_t val);
  56   void take_trap(trap_t t, bool noisy);
  57   void disasm(insn_t insn, reg_t pc);
  58
  59   friend class sim_t;
  60 };
  61
  62 #endif