riscv/processor.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_PROCESSOR_H
   4 #define _RISCV_PROCESSOR_H
   5
   6 #include "decode.h"
   7 #include <cstring>
   8 #include "trap.h"
   9 #include "config.h"
  10 #include <map>
  11
  12 class processor_t;
  13 class mmu_t;
  14 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  15 class sim_t;
  16
  17 // this class represents one processor in a RISC-V machine.
  18 class processor_t
  19 {
  20 public:
  21   processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
  22   ~processor_t();
  23
  24   void reset(bool value);
  25   void step(size_t n, bool noisy); // run for n cycles
  26   void deliver_ipi(); // register an interprocessor interrupt
  27   bool running() { return run; }
  28   void set_pcr(int which, reg_t val);
  29   void set_interrupt(int which, bool on);
  30   reg_t get_pcr(int which);
  31   mmu_t* get_mmu() { return &mmu; }
  32
  33   void register_insn(uint32_t match, uint32_t mask, insn_func_t rv32, insn_func_t rv64);
  34
  35 private:
  36   sim_t& sim;
  37   mmu_t& mmu; // main memory is always accessed via the mmu
  38
  39   // user-visible architected state
  40   reg_t pc;
  41   regfile_t<reg_t, NXPR, true> XPR;
  42   regfile_t<freg_t, NFPR, false> FPR;
  43   reg_t cycle;
  44
  45   // privileged control registers
  46   reg_t epc;
  47   reg_t badvaddr;
  48   reg_t evec;
  49   reg_t pcr_k0;
  50   reg_t pcr_k1;
  51   reg_t cause;
  52   reg_t tohost;
  53   reg_t fromhost;
  54   uint32_t id;
  55   uint32_t sr; // only modify the status register using set_pcr()
  56   uint32_t fsr;
  57   uint32_t count;
  58   uint32_t compare;
  59
  60   bool run; // !reset
  61
  62   struct opcode_map_entry_t
  63   {
  64     uint32_t match;
  65     uint32_t mask;
  66     insn_func_t rv32;
  67     insn_func_t rv64;
  68   };
  69   unsigned opcode_bits;
  70   std::multimap<uint32_t, opcode_map_entry_t> opcode_map;
  71
  72   void take_interrupt(); // take a trap if any interrupts are pending
  73   void set_fsr(uint32_t val); // set the floating-point status register
  74   void take_trap(reg_t t, bool noisy); // take an exception
  75   void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction
  76
  77   friend class sim_t;
  78   friend class mmu_t;
  79   friend class htif_isasim_t;
  80
  81   #define DECLARE_INSN(name, match, mask) \
  82     reg_t rv32_ ## name(insn_t insn, reg_t pc); \
  83     reg_t rv64_ ## name(insn_t insn, reg_t pc);
  84   #include "opcodes.h"
  85   #undef DECLARE_INSN
  86
  87   insn_func_t decode_insn(insn_t insn);
  88   reg_t illegal_instruction(insn_t insn, reg_t pc);
  89 };
  90
  91 #endif