riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "htif.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13
  14 volatile bool ctrlc_pressed = false;
  15 static void handle_signal(int sig)
  16 {
  17   if (ctrlc_pressed)
  18     exit(-1);
  19   ctrlc_pressed = true;
  20   signal(sig, &handle_signal);
  21 }
  22
  23 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
  24              const std::vector<std::string>& args)
  25   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
  26     current_step(0), current_proc(0), debug(false), gdbserver(NULL)
  27 {
  28   signal(SIGINT, &handle_signal);
  29   // allocate target machine's memory, shrinking it as necessary
  30   // until the allocation succeeds
  31   size_t memsz0 = (size_t)mem_mb << 20;
  32   size_t quantum = 1L << 20;
  33   if (memsz0 == 0)
  34     memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
  35
  36   memsz = memsz0;
  37   while ((mem = (char*)calloc(1, memsz)) == NULL)
  38     memsz = (size_t)(memsz*0.9)/quantum*quantum;
  39
  40   if (memsz != memsz0)
  41     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
  42             (unsigned long)memsz, (unsigned long)memsz0);
  43
  44   /* Copy Debug ROM into the end of the allocated block, because we surely
  45    * didn't succeed in allocation 0xfffffffff800 bytes. */
  46   /* TODO: Once everything uses the new memory map, just put this at the
  47    * address that it actually belongs at. */
  48   memcpy(mem + memsz - debug_rom_raw_len, debug_rom_raw, debug_rom_raw_len);
  49
  50   debug_mmu = new mmu_t(this, NULL);
  51
  52   for (size_t i = 0; i < procs.size(); i++) {
  53     procs[i] = new processor_t(isa, this, i);
  54     if (halted)
  55       procs[i]->enter_debug_mode(DCSR_CAUSE_HALT);
  56   }
  57
  58   rtc.reset(new rtc_t(procs));
  59   make_config_string();
  60 }
  61
  62 sim_t::~sim_t()
  63 {
  64   for (size_t i = 0; i < procs.size(); i++)
  65     delete procs[i];
  66   delete debug_mmu;
  67   free(mem);
  68 }
  69
  70 int sim_t::run()
  71 {
  72   if (!debug && log)
  73     set_procs_debug(true);
  74   while (htif->tick())
  75   {
  76     if (debug || ctrlc_pressed)
  77       interactive();
  78     else
  79       step(INTERLEAVE);
  80     if (gdbserver) {
  81         gdbserver->handle();
  82     }
  83   }
  84   return htif->exit_code();
  85 }
  86
  87 void sim_t::step(size_t n)
  88 {
  89   for (size_t i = 0, steps = 0; i < n; i += steps)
  90   {
  91     steps = std::min(n - i, INTERLEAVE - current_step);
  92     procs[current_proc]->step(steps);
  93
  94     current_step += steps;
  95     if (current_step == INTERLEAVE)
  96     {
  97       current_step = 0;
  98       procs[current_proc]->yield_load_reservation();
  99       if (++current_proc == procs.size()) {
 100         current_proc = 0;
 101         rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 102       }
 103
 104       htif->tick();
 105     }
 106   }
 107 }
 108
 109 bool sim_t::running()
 110 {
 111   for (size_t i = 0; i < procs.size(); i++)
 112     if (procs[i]->running())
 113       return true;
 114   return false;
 115 }
 116
 117 void sim_t::set_debug(bool value)
 118 {
 119   debug = value;
 120 }
 121
 122 void sim_t::set_log(bool value)
 123 {
 124   log = value;
 125 }
 126
 127 void sim_t::set_histogram(bool value)
 128 {
 129   histogram_enabled = value;
 130   for (size_t i = 0; i < procs.size(); i++) {
 131     procs[i]->set_histogram(histogram_enabled);
 132   }
 133 }
 134
 135 void sim_t::set_procs_debug(bool value)
 136 {
 137   for (size_t i=0; i< procs.size(); i++)
 138     procs[i]->set_debug(value);
 139 }
 140
 141 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 142 {
 143   if (addr + len < addr)
 144     return false;
 145   return bus.load(addr, len, bytes);
 146 }
 147
 148 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 149 {
 150   if (addr + len < addr)
 151     return false;
 152   return bus.store(addr, len, bytes);
 153 }
 154
 155 void sim_t::make_config_string()
 156 {
 157   reg_t rtc_addr = EXT_IO_BASE;
 158   bus.add_device(rtc_addr, rtc.get());
 159
 160   const int align = 0x1000;
 161   reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
 162   reg_t cpu_size = align;
 163
 164   uint32_t reset_vec[8] = {
 165     0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
 166     0x00028067,                         //   jump straight to DRAM_BASE
 167     0x00000000,                         // reserved
 168     0,                                  // config string pointer
 169     0, 0, 0, 0                          // trap vector
 170   };
 171   reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
 172
 173   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 174
 175   std::stringstream s;
 176   s << std::hex <<
 177         "platform {\n"
 178         "  vendor ucb;\n"
 179         "  arch spike;\n"
 180         "};\n"
 181         "rtc {\n"
 182         "  addr 0x" << rtc_addr << ";\n"
 183         "};\n"
 184         "ram {\n"
 185         "  0 {\n"
 186         "    addr 0x" << DRAM_BASE << ";\n"
 187         "    size 0x" << memsz << ";\n"
 188         "  };\n"
 189         "};\n"
 190         "core {\n";
 191   for (size_t i = 0; i < procs.size(); i++) {
 192     s <<
 193         "  " << i << " {\n"
 194         "    " << "0 {\n" << // hart 0 on core i
 195         "      isa " << procs[i]->isa_string << ";\n"
 196         "      timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
 197         "      ipi 0x" << cpu_addr << ";\n"
 198         "    };\n"
 199         "  };\n";
 200     bus.add_device(cpu_addr, procs[i]);
 201     cpu_addr += cpu_size;
 202   }
 203   s <<  "};\n";
 204
 205   config_string = s.str();
 206   rom.insert(rom.end(), config_string.begin(), config_string.end());
 207   rom.resize((rom.size() / align + 1) * align);
 208
 209   boot_rom.reset(new rom_device_t(rom));
 210   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 211 }