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[riscv-isa-sim.git] / riscv / sv.cc

#include "sv.h"
#include "sv_decode.h"
#include "processor.h"

int get_bitwidth(uint8_t elwidth, int xlen)
{
  switch (elwidth) {
      case 0: return xlen;
      case 1: return 8;
      case 2: return 16;
      default: return 32;
  }
}

uint8_t maxelwidth(uint8_t wid1, uint8_t wid2)
{
    if (wid1 == 0 || wid2 == 0) {
        return 0;
    }
    return std::max(wid1, wid2);
}

/* convenience routines to map from compact 8-bit to 16-bit format,
 * for use in new VBLOCK format
 */
void sv_regmap_8to16(union sv_reg_csr_entry8 const& r8,
                     union sv_reg_csr_entry &r16)
{
    r16.b.regkey  = r8.b.regkey;
    r16.b.elwidth = r8.b.elwidth;
    r16.b.type    = r8.b.type;
    r16.b.regidx  = r8.b.regkey << 2; // multiply by 4, no room for 6 bits
    r16.b.isvec   = 1;                // has to be a vector
}

void sv_predmap_8to16(union sv_pred_csr_entry8 const& r8,
                      union sv_pred_csr_entry &r16,
                      uint64_t table_idx)
{
    r16.b.regkey  = r8.b.regkey;
    r16.b.zero    = r8.b.zero;
    r16.b.inv     = r8.b.inv;
    r16.b.type    = r8.b.type;
    r16.b.regidx  = table_idx + 9; // 8-bit format starts at x9
    r16.b.ffirst  = 0;             // no room, whoops.
}

/* increments the sub-offset appropriately in a FSM-based
   version of a twin-nested for-loop:
     for (suboffs = 0; suboffs < subvl; suboffs++) {
     ... doooo stuuuuff (python would use "yield" here)
     }
     suboffs = 0; // reset to zero after "loop"
*/
bool inc_offs(int vlen, int subvl, int &suboffs)
{
    suboffs++;
    if (suboffs < subvl) {
        return false; // outer loop should not increment
    }
    suboffs = 0; // reset the sub-offs
    return true; // indicates outer (VL) loop should increment
}

sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled,
            insn_bits_t bits, unsigned int f,
            int _xlen, int _src_flen, int _dest_flen,
            uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
            uint64_t &p_sp, uint64_t *p_im,
            int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
            int *o_imm,
            int *s_offs,
            bool _sign) :
            insn_t(bits), p(pr), src_bitwidth(0),
            xlen(_xlen), src_flen(_src_flen), dest_flen(_dest_flen),
            sv_enabled(_sv_enabled), signextended(_sign),
            vloop_continue(false),
            at_least_one_reg_vectorised(false), fimap(f),
            offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
            offs_sp(o_sp),
            offs_imm(o_imm),
            suboffs(s_offs), 
            prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3), psp(p_sp),
            save_branch_addr(0)
{
    // work out the source element width based on what is used
    // note that this has to match with id_regs.py patterns

    unsigned int bm=2;
    for (int i = 1; i < 12; i++, bm<<=1)
    {
        sv_reg_entry* r = NULL;
        if (bm == (REG_RS1 & fimap)) {
             r = get_regentry(insn_t::rs1(), true);
        } else if (bm == (REG_RS2 & fimap)) {
             r = get_regentry(insn_t::rs2(), true);
        } else if (bm == (REG_RS3 & fimap)) {
             r = get_regentry(insn_t::rs3(), true);
        } else if (bm == (REG_RVC_RS1 & fimap)) {
             r = get_regentry(insn_t::rvc_rs1(), true);
        } else if (bm == (REG_RVC_RS2 & fimap)) {
             r = get_regentry(insn_t::rvc_rs2(), true);
        } else if (bm == (REG_RVC_RS1S & fimap)) {
             r = get_regentry(insn_t::rvc_rs1s(), true);
        } else if (bm == (REG_RVC_RS2S & fimap)) {
             r = get_regentry(insn_t::rvc_rs2s(), true);
        } else if (bm == (REG_FRS1 & fimap)) {
             r = get_regentry(insn_t::rs1(), false);
        } else if (bm == (REG_FRS2 & fimap)) {
             r = get_regentry(insn_t::rs2(), false);
        } else if (bm == (REG_FRS3 & fimap)) {
             r = get_regentry(insn_t::rs3(), false);
        }
        if (r ==  NULL || !r->active) {
            continue;
        }
        uint8_t elwidth = r->elwidth;
        uint8_t bitwidth = get_bitwidth(elwidth, _xlen);
        src_bitwidth = std::max(src_bitwidth, bitwidth);
    }
}

sv_pred_entry* sv_insn_t::get_predentry(uint64_t reg, bool intreg)
{
  // okaay so first determine which map to use.  intreg is passed
  // in (ultimately) from id_regs.py's examination of the use of
  // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed
  // in from sv_insn_t::fimap...
  sv_pred_entry *r;
  if (intreg)
  {
    return &p->get_state()->sv().sv_pred_int_tb[reg];
  }
  else
  {
    return &p->get_state()->sv().sv_pred_fp_tb[reg];
  }
}

sv_reg_entry* sv_insn_t::get_regentry(uint64_t reg, bool intreg)
{
  // okaay so first determine which map to use.  intreg is passed
  // in (ultimately) from id_regs.py's examination of the use of
  // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed
  // in from sv_insn_t::fimap...
  sv_reg_entry *r;
  if (intreg)
  {
    return &p->get_state()->sv().sv_int_tb[reg];
  }
  else
  {
    return &p->get_state()->sv().sv_fp_tb[reg];
  }
}

bool sv_insn_t::sv_check_reg(bool intreg, uint64_t reg)
{
  sv_reg_entry *r = get_regentry(reg, intreg);
  if (r->elwidth != 0)
  {
    // XXX raise exception
  }
  if (r->active && r->isvec)
  {
    fprintf(stderr, "checkreg: %ld active isvec\n", reg);
    at_least_one_reg_vectorised = true;
    return true;
  }
  if (r->active)
  {
    fprintf(stderr, "checkreg: %ld active !vec\n", reg);
  }
  return false;
}

/* this is the "remap" function.  note that registers can STILL BE REDIRECTED
 * yet NOT BE MARKED AS A VECTOR.
 *
 * reg 5 -> active=false, regidx=XX, isvec=XX     -> returns 5
 * reg 5 -> active=true , regidx=35, isvec=false  -> returns 35
 * reg 5 -> active=true , regidx=35, isvec=true   -> returns 35 *PLUS LOOP*
 *
 * so it is possible for example to use the remap system for C  instructions
 * to get access to the *full* range of registers x0..x63 (yes 63 because
 * SV doubles both the int and fp regfile sizes), by setting
 * "active=true, isvec=false" for any of x8..x15
 *
 * where "active=true, isvec=true" this is the "expected" behaviour
 * of SV.  it's "supposed" to "just" be a vectorisation API. it isn't:
 * it's quite a bit more.
 */
reg_spec_t sv_insn_t::remap(uint64_t reg, bool intreg, int *voffs, int *subo)
{
  reg_spec_t spec = {reg, NULL};
  // okaay so first determine which map to use.  intreg is passed
  // in (ultimately) from id_regs.py's examination of the use of
  // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed
  // in from sv_insn_t::fimap...
  sv_reg_entry *r = get_regentry(reg, intreg);

  // next we check if this entry is active.  if not, the register
  // is not being "redirected", so just return the actual reg.
  if (!r->active)
  {
    return spec; // not active: return as-is
  }
  vloop_continue = true;

  // next we go through the lookup table.  *THIS* is why the
  // sv_reg_entry table is 32 entries (5-bit) *NOT* 6 bits
  // the *KEY* (reg) is 5-bit, the *VALUE* (actual target reg) is 6-bit
  // XXX TODO: must actually double NXPR and NXFR in processor.h to cope!!
  reg = r->regidx;

  // now we determine if this is a scalar/vector: if it's scalar
  // we return the re-mapped register...
#if 0
  if (!r->isvec) // scalar
  {
    return spec;
  }
#endif
  vloop_continue = true;

  // aaand now, as it's a "vector", FINALLY we can pass the loop-offset
  spec.reg = reg; //+ *voffs;
  spec.offset = voffs;
  spec.suboff = subo;
  spec.isvec = r->isvec;
  spec.signextend = signextended;
  return spec;
}

/* gets the predication value (if active).  returns all-1s if not active
 * also returns whether zeroing is enabled/disabled for this register.
 *
 * uses the same sort of lookup logic as remap:
 *
 * - first thing to note is, there is one CSR table for FP and one for INT
 *   (so, FP regs can be predicated separately from INT ones)
 * - redirection occurs if the CSR entry for the register is "active".
 * - inversion of the predication can be set (so it's possible to have
 *   the same actual register value be unchanged yet be referred to by
 *   *TWO* redirections, one with inversion, one with not).
 *
 * note that this function *actually* returns the value of the (integer)
 * register file, hence why processor_t has to be passed in
 *
 * note also that *even scalar* ops will be predicated (i.e. if a register
 * has been set active=true and isvec=false in sv_int_tb or sv_fp_tb).
 * the way to ensure that scalar ops are not predicated is: set VLEN=0,
 * set active=false in sv_int_tb/sv_fp_tb for that register, or switch off
 * the predication for that register (sv_pred_int_tb/sv_pred_fb_tb).
 *
 * note also that the hard limit on SV maximum vector length is actually
 * down to the number of bits in the predication i.e. the bitwidth of integer
 * registers (i.e. XLEN bits).
 */
reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing)
{
  sv_reg_entry *pr = get_regentry(reg, intreg);
  if (!pr->active)
  {
    return ~0x0; // *REGISTER* not active: return all-1s (unconditional "on")
  }
  sv_pred_entry *r = get_predentry(reg, intreg);
  if (!r->active)
  {
    return ~0x0; // *PREDICATION* not active: return all-1s (unconditional "on")
  }
  zeroing = r->zero;
  fprintf(stderr, "predicate read %ld -> %ld\n", reg, r->regidx);
  reg = r->regidx;
  reg_spec_t rs = {reg, NULL};
  reg_t pred = p->s.READ_REG(rs); // macros go through processor_t state
  if (r->inv)
  {
    return ~pred;
  }
  return pred;
}

// XXX WARNING: this fn does NOT invert the predicate (if r->inv return ~pred)
reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing, bool &inv)
{
  sv_reg_entry *pr = get_regentry(reg, intreg);
  if (!pr->active)
  {
    return ~0x0; // *REGISTER* not active: return all-1s (unconditional "on")
  }
  sv_pred_entry *r = get_predentry(reg, intreg);
  if (!r->active)
  {
    return ~0x0; // *PREDICATION* not active: return all-1s (unconditional "on")
  }
  zeroing = r->zero;
  inv = r->inv;
  fprintf(stderr, "predicate read %ld -> %ld\n", reg, r->regidx);
  reg = r->regidx;
  reg_spec_t rs = {reg, NULL};
  reg_t predicate = p->s.READ_REG(rs); // macros go through processor_t state
  return predicate;
}

reg_spec_t sv_insn_t::predicated(reg_spec_t const& spec, uint64_t pred)
{
    reg_spec_t res = spec;
    if (spec.offset == NULL)
    {
        return res;
    }
    if (pred & (1<<p->s.pred_remap(res.reg, *spec.offset)))
    {
        return res;
    }
    fprintf(stderr, "predication %ld %d %lx\n", spec.reg, (*spec.offset), pred);
    res.reg = 0;
    res.offset = 0;
    res.suboff = 0;
    res.isvec = spec.isvec;
    return res;
}

bool sv_insn_t::stop_vloop(void)
{
    return (p->get_state()->sv().vl == 0) || !vloop_continue;
}


/* c_lwsp's immediate offset is turned into a Vector "unit stride" if
 * x2 (sp by convention) is marked as vectorised.
 *
 */
uint64_t sv_insn_t::_rvc_spoffs_imm(uint64_t elwidth, uint64_t offs)
{
  sv_reg_entry *r = get_regentry(X_SP, 1);
  if (!r->active)
  {
    return offs;
  }
  vloop_continue = true;
  reg_t reg = r->regidx;
  if (!r->isvec)
  {
    return offs;
  }
  offs += (*offs_imm) * elwidth;

  return offs;
}

// for use in predicated branches. sets bit N if val=true; clears bit N if false
uint64_t sv_insn_t::rd_bitset(reg_t reg, int bit, bool set)
{
    uint64_t val = STATE.XPR[reg];
    if (set) {
        val |= (1UL<<bit);
    } else {
        val &= ~(1UL<<bit);
    }
    STATE.XPR.write(reg, val);
    return val;
}

/* called by the instruction: in scalar mode it performs the branch.
   in SV mode, the fact that the bxx.h even tried to call setpc is
   taken to mean that the compare succeeded, and save_branch_rd is
   used instead to accumulate that information [or the target_reg
   used instead, and copied into save_branch_rd]

   at the **END** of the vector loop (back in insn_template_sv.cc)
   the *accumulated* results in save_branch_rd are tested to see
   if they *all* succeeded, and if so *then* the branch is taken.

   TODO: the loop has to be modified to be aware of SUBVL, because
   only if *all* subvector elements succeed is the save_branch_rd
   bit allowed to be set.
*/
void sv_insn_t::setpc(int xlen, int vlen, reg_t &npc, reg_t addr, uint64_t offs,
                      reg_t *target_reg, bool zeroing, bool inv)
{
    save_branch_addr = addr;
    if (not at_least_one_reg_vectorised) // scalar-scalar: make the branch
    {
        _set_pc(addr);
        return;
    }
    if (target_reg != NULL) {
        reg_spec_t rs = {*target_reg, NULL};
        fprintf(stderr, "setpc pre rd %ld v %lx pred %lx\n",
                        *target_reg, p->s.READ_REG(rs), prs1);
    }
    if (target_reg) {
        offs = p->s.pred_remap(*target_reg, offs);
    }
    if ((1<<offs) & prs1)
    {
        if (target_reg) {
            save_branch_rd = rd_bitset(*target_reg, offs, !zeroing);
        } else {
            if (zeroing)
                save_branch_rd &= ~(1UL<<offs);
            else
                save_branch_rd |= (1UL<<offs);
        }
    }
    else if (inv) // target pred, meaning of inv bit is overloaded
    {
      vloop_continue = false;
    }
    fprintf(stderr, "setpc %lx offs %ld predicate %lx rs1 %ld rs2 %ld\n",
            save_branch_rd, offs, prs1,
            p->s.READ_REG(rs1()), p->s.READ_REG(rs2()));
}

uint8_t sv_insn_t::reg_elwidth(reg_t reg, bool intreg)
{
    sv_reg_entry *r = get_regentry(reg, intreg);
    if (r->active) {
        return r->elwidth;
    }
    return 0;
}

uint64_t sv_csr_t::regpush(uint16_t csrval, int len, bool top)
{
    // when csrval == 0 it means "pop".
    // when reg != 0 and an existing entry exists, it means "change reg"
    // when reg != 0 and an existing entry doesn't exist, it means "push"
    // push/pop are to top when top is true, otherwise to bottom.
    uint64_t reg = get_field(csrval, 0x1f);
    int idx = 0;
    int topstack = -1;
    for (idx = 0; idx < len; idx++)
    {
        if (sv_csrs[idx].u == 0) {
            topstack = idx; // used to count to end (for pop/push)
            break;
        } else if (reg != 0 && sv_csrs[idx].b.regkey == reg) {
            sv_csrs[idx].u = csrval; // change reg
            return 0; // no popping
        }
    }
    // ok entry not found, is reg==0, means "pop"
    if (csrval == 0) {
        uint64_t popped = 0;
        if (top) {
            if (topstack == 0) {
                return 0;
            }
            topstack -= 1;
            uint64_t popped = sv_csrs[topstack].u;
            sv_csrs[topstack].u = 0;
            fprintf(stderr, "regcsr clr %d\n", topstack);
        } else {
            uint64_t popped = sv_csrs[0].u;
            for (idx = 0; idx < topstack-1; idx++) {
                sv_csrs[idx].u = sv_csrs[idx+1].u;
                fprintf(stderr, "regcsr clr shuffle %d %d\n", idx, idx+1);
            }
            sv_csrs[topstack].u = 0;
            fprintf(stderr, "regcsr clr %d\n", topstack);
        }
        return popped;
    }
    // ok entry not found, reg != 0, means "push", are we pushing to top?
    if (top) {
        if (topstack == len-1) { // not enough room
            uint64_t popped = sv_csrs[0].u;
            for (idx = 0; idx < topstack-1; idx++) {
                sv_csrs[idx].u = sv_csrs[idx+1].u;
                fprintf(stderr, "regcsr shuffle %d %d\n", idx, idx+1);
            }
            sv_csrs[topstack].u = csrval;
            fprintf(stderr, "regcsr set %d %x\n", topstack, csrval);
            return popped;
        } else {
            sv_csrs[topstack].u = csrval;
            fprintf(stderr, "regcsr set %d %x\n", topstack, csrval);
            return 0;
        }
    }
    // no, we're pushing at bottom
    uint64_t popped = 0;
    if (topstack == len-1) { // not enough room
        popped = sv_csrs[topstack].u; // top's going to get wiped
    }
    for (idx = topstack; idx > 0; idx--) {
        sv_csrs[idx].u = sv_csrs[idx-1].u;
    }
    sv_csrs[0].u = csrval; // put in at bottom
    return popped;
}