riscv/sv.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_SIMPLE_V_H
   4 #define _RISCV_SIMPLE_V_H
   5
   6 #include "decode.h"
   7
   8 // useful macros for constructing SV reg and predicate CSR CAM entries
   9 #define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \
  10   (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15))
  11 #define SV_PRED_CSR(type, regkey, zero, inv, regidx, ffirst) \
  12   (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (ffirst<<15))
  13
  14 // this table is for the CSRs (4? for RV32E, 16 for other types)
  15 // it's a CAM that's used to generate 2 tables (below)
  16 // just as in RV, writing to entries in this CAM *clears*
  17 // all entries with a higher index
  18 union sv_reg_csr_entry {
  19     struct {
  20         uint64_t     regkey : 5; // 5 bits
  21         unsigned int elwidth: 2; // 0=dflt, 1=dflt/2, 2=dflt*2 3=8-bit
  22         unsigned int type   : 1; // 1=INT, 0=FP
  23         uint64_t     regidx : 7; // yes 6 bits
  24         unsigned int isvec  : 1; // vector=1, scalar=0
  25     } b;
  26     unsigned short u;
  27 };
  28
  29 // the 8-bit (compact) variant
  30 union sv_reg_csr_entry8 {
  31     struct {
  32         uint64_t     regkey : 5; // 5 bits
  33         unsigned int elwidth: 2; // 0=dflt, 1=dflt/2, 2=dflt*2 3=8-bit
  34         unsigned int type   : 1; // 1=INT, 0=FP
  35     } b;
  36     unsigned char u;
  37 };
  38
  39 void sv_regmap_8to16(union sv_reg_csr_entry8 const& r8,
  40                      union sv_reg_csr_entry8 &r16);
  41
  42 // TODO: define separate SV CSRs for M-mode and S-Mode
  43 // M-Mode and S-Mode will need a minimum of 2 for int-only
  44 // platforms, and a minimum of 4 for int/fp.
  45 // this to be able to use SV for contiguous register save/restore
  46 // in around 2 instructions rather than massive blocks of 31
  47 #define SV_UCSR_SZ 16 // TODO: only 4? for RV32?
  48 #define SV_MCSR_SZ 4
  49 #define SV_SCSR_SZ 4
  50
  51 // this is the "unpacked" table, generated from the CAM above
  52 // there are 2 of them: one for FP, one for INT regs.
  53 // one sv_reg_entry is required per FP *and* per INT reg.
  54 // note that regidx is 6 bits however we actually only have
  55 // 32 entries.  reason: the *actual* number of registers is doubled
  56 // in SV however the instruction is STILL ONLY 5 BITS.
  57 typedef struct {
  58     unsigned int elwidth: 2; // 0=8-bit, 1=dflt, 2=dflt/2 3=dflt*2
  59     uint64_t     regidx : 7; // yes 7 bits.
  60     unsigned int isvec  : 1; // vector=1, scalar=0
  61     unsigned int active : 1; // enabled=1, disabled=0
  62 } sv_reg_entry;
  63
  64 union sv_pred_csr_entry {
  65     struct {
  66         uint64_t     regkey: 5; // 5 bits
  67         unsigned int zero  : 1; // zeroing=1, skipping=0
  68         unsigned int inv   : 1; // inversion=1
  69         unsigned int type  : 1; // 1=INT, 0=FP
  70         uint64_t     regidx: 7; // 7 bits
  71         unsigned int ffirst: 1; // Fail on first
  72     } b;
  73     unsigned short u;
  74 };
  75
  76 // the 8-bit (compact) variant
  77 union sv_pred_csr_entry8 {
  78     struct {
  79         uint64_t     regkey: 5; // 5 bits
  80         unsigned int zero  : 1; // zeroing=1, skipping=0
  81         unsigned int inv   : 1; // inversion=1
  82         unsigned int type  : 1; // 1=INT, 0=FP
  83     } b;
  84     unsigned char u;
  85 };
  86
  87 void sv_predmap_8to16(union sv_reg_csr_entry8 const& r8,
  88                       union sv_reg_csr_entry8 &r16,
  89                       uint64_t table_idx);
  90
  91 typedef struct {
  92     uint64_t     regkey: 5; // 5 bits
  93     unsigned int zero  : 1; // zeroing=1, skipping=0
  94     unsigned int inv   : 1; // inversion=1
  95     uint64_t     regidx: 7; // 7 bits
  96     unsigned int active: 1; // enabled=1, disabled=0
  97     unsigned int ffirst: 1; // Fail on first
  98 } sv_pred_entry;
  99
 100 bool sv_check_reg(bool intreg, uint64_t reg);
 101
 102 typedef struct {
 103     uint64_t regidx: 7; // actual i.e. real register (0-127)
 104     unsigned int shape: 2; // which shape register to use
 105     bool pred;
 106 } sv_remap_t;
 107
 108 typedef struct {
 109     int xsz;
 110     int ysz;
 111     int zsz;
 112     int offs;
 113     int permute;
 114     uint8_t map[128];
 115     void setup_map();
 116 } sv_shape_t;
 117
 118 #define SV_REMAP_REGIDX0 (0x7f)
 119 #define SV_REMAP_PRED0 (0x80)
 120 #define SV_REMAP_REGIDX1 (0x7f<<8)
 121 #define SV_REMAP_PRED1 (0x800)
 122 #define SV_REMAP_REGIDX2 (0x7f<<16)
 123 #define SV_REMAP_PRED2 (0x8000)
 124 #define SV_REMAP_SHAPE0 (0x3<<24)
 125 #define SV_REMAP_SHAPE1 (0x3<<26)
 126 #define SV_REMAP_SHAPE2 (0x3<<28)
 127 #define SV_SHAPE_XDIM (0x7f)
 128 #define SV_SHAPE_YDIM (0x7f<<8)
 129 #define SV_SHAPE_ZDIM (0x7f<<16)
 130 #define SV_SHAPE_PERM (0x7<<24)
 131
 132 #define SV_SHAPE_PERM_XYZ 0
 133 #define SV_SHAPE_PERM_XZY 1
 134 #define SV_SHAPE_PERM_YXZ 2
 135 #define SV_SHAPE_PERM_YZX 3
 136 #define SV_SHAPE_PERM_ZXY 4
 137 #define SV_SHAPE_PERM_ZYX 5
 138
 139 #define SV_STATE_VL (0x1f)
 140 #define SV_STATE_MVL (0x1f<<6)
 141 #define SV_STATE_SRCOFFS (0x1f<<12)
 142 #define SV_STATE_DESTOFFS (0x1f<<18)
 143 #define SV_STATE_SUBVL (0x3<<24)
 144 #define SV_STATE_DSVOFFS (0x3<<26)
 145
 146 #define SV_CFG_BANK (0x7)
 147 #define SV_CFG_SIZE (0x3<<3)
 148
 149 bool inc_offs(int vlen, int subvl, int &suboffs);
 150
 151 #endif