ok this is tricky: an extra parameter has to be passed into sv_insn_t::remap
[riscv-isa-sim.git] / riscv / sv_decode.h
1 // See LICENSE for license details.
2
3 #ifndef _RISCV_SV_DECODE_H
4 #define _RISCV_SV_DECODE_H
5
6 #include "sv.h"
7 #include "decode.h"
8
9 #define REG_RD 0x1
10 #define REG_RS1 0x2
11 #define REG_RS2 0x4
12 #define REG_RS3 0x8
13
14 class sv_insn_t: public insn_t
15 {
16 public:
17 sv_insn_t(insn_bits_t bits, int& v, unsigned int f) :
18 insn_t(bits), voffs(v), fimap(f) {}
19 uint64_t rd () { return remap(insn_t::rd (), fimap & REG_RD); }
20 uint64_t rs1() { return remap(insn_t::rs1(), fimap & REG_RS1); }
21 uint64_t rs2() { return remap(insn_t::rs2(), fimap & REG_RS2); }
22 uint64_t rs3() { return remap(insn_t::rs3(), fimap & REG_RS3); }
23 private:
24 int &voffs;
25 unsigned int fimap;
26 // remaps the register through the lookup table.
27 // will need to take the current loop index/offset somehow
28 uint64_t remap(uint64_t reg, bool isint);
29 };
30
31 #endif