1 // See LICENSE for license details.
3 #ifndef _RISCV_SV_DECODE_H
4 #define _RISCV_SV_DECODE_H
14 class sv_insn_t
: public insn_t
17 sv_insn_t(insn_bits_t bits
, unsigned int f
) :
18 insn_t(bits
), fimap(f
),
19 cached_rd(0xff), cached_rs1(0xff),
20 cached_rs2(0xff), cached_rs3(0xff),
21 offs_rd(0), offs_rs1(0),
22 offs_rs2(0), offs_rs3(0) {}
24 { return _remap(insn_t::rd (), fimap
& REG_RD
, offs_rd
, cached_rd
); }
26 { return _remap(insn_t::rs1(), fimap
& REG_RS1
, offs_rs1
, cached_rs1
); }
28 { return _remap(insn_t::rs2(), fimap
& REG_RS2
, offs_rs2
, cached_rs2
); }
30 { return _remap(insn_t::rs3(), fimap
& REG_RS3
, offs_rs3
, cached_rs3
); }
32 void reset_caches(void)
49 // remaps the register through the lookup table.
50 // will need to take the current loop index/offset somehow
51 uint64_t remap(uint64_t reg
, bool isint
, int &offs
);
53 // cached version of remap: if remap is called multiple times
54 // by an emulated instruction it would increment the loop offset
55 // before it's supposed to.
56 uint64_t _remap(uint64_t reg
, bool isint
, int &offs
, uint64_t &cached
)
60 cached
= remap(reg
, isint
, offs
);