riscv/sv_decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_SV_DECODE_H
   4 #define _RISCV_SV_DECODE_H
   5
   6 #include "sv.h"
   7 #include "decode.h"
   8 #include "processor.h"
   9
  10 #define REG_RD 0x1
  11 #define REG_RS1 0x2
  12 #define REG_RS2 0x4
  13 #define REG_RS3 0x8
  14 #define REG_RVC_RS1 0x10
  15 #define REG_RVC_RS2 0x20
  16 #define REG_RVC_RS1S 0x40
  17 #define REG_RVC_RS2S 0x80
  18
  19
  20 class sv_insn_t: public insn_t
  21 {
  22 public:
  23   sv_insn_t(processor_t *pr, insn_bits_t bits, unsigned int f,
  24             uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3) :
  25             insn_t(bits), p(pr), vloop_continue(false), fimap(f),
  26             cached_rd(0xff), cached_rs1(0xff),
  27             cached_rs2(0xff), cached_rs3(0xff),
  28             offs_rd(0), offs_rs1(0),
  29             offs_rs2(0), offs_rs3(0),
  30             new_offs_rd(0), new_offs_rs1(0),
  31             new_offs_rs2(0), new_offs_rs3(0),
  32             prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3) {}
  33   uint64_t rd () { return predicated(_rd (), offs_rd , prd); }
  34   uint64_t rs1() { return predicated(_rs1(), offs_rs1, prs1); }
  35   uint64_t rs2() { return predicated(_rs2(), offs_rs2, prs2); }
  36   uint64_t rs3() { return predicated(_rs3(), offs_rs3, prs3); }
  37   uint64_t rvc_rs1 () { return predicated(_rvc_rs1 (), offs_rs1, prs1); }
  38   uint64_t rvc_rs1s() { return predicated(_rvc_rs1s(), offs_rs1, prs1); }
  39   uint64_t rvc_rs2 () { return predicated(_rvc_rs2 (), offs_rs2, prs2); }
  40   uint64_t rvc_rs2s() { return predicated(_rvc_rs2s(), offs_rs2, prs2); }
  41
  42   uint64_t _rd () { return _remap(insn_t::rd (), fimap & REG_RD ,
  43                                   offs_rd , cached_rd, new_offs_rd); }
  44   uint64_t _rs1() { return _remap(insn_t::rs1(), fimap & REG_RS1,
  45                                   offs_rs1, cached_rs1, new_offs_rs1); }
  46   uint64_t _rs2() { return _remap(insn_t::rs2(), fimap & REG_RS2,
  47                                   offs_rs2, cached_rs2, new_offs_rs2); }
  48   uint64_t _rs3() { return _remap(insn_t::rs3(), fimap & REG_RS3,
  49                                   offs_rs3, cached_rs3, new_offs_rs3); }
  50   uint64_t _rvc_rs1 () { return _remap(insn_t::rvc_rs1(), fimap & REG_RVC_RS1,
  51                                        offs_rs1, cached_rs1, new_offs_rs1); }
  52   uint64_t _rvc_rs1s() { return _remap(insn_t::rvc_rs1s(), fimap & REG_RVC_RS1S,
  53                                        offs_rs1, cached_rs1, new_offs_rs1); }
  54   uint64_t _rvc_rs2 () { return _remap(insn_t::rvc_rs2(), fimap & REG_RVC_RS2,
  55                                        offs_rs2, cached_rs2, new_offs_rs2); }
  56   uint64_t _rvc_rs2s() { return _remap(insn_t::rvc_rs2s(), fimap & REG_RVC_RS2S,
  57                                        offs_rs2, cached_rs2, new_offs_rs2); }
  58
  59   void reset_caches(void)
  60   {
  61     cached_rd = 0xff;
  62     cached_rs1 = 0xff;
  63     cached_rs2 = 0xff;
  64     cached_rs3 = 0xff;
  65     offs_rd = new_offs_rd;
  66     offs_rs1 = new_offs_rs1;
  67     offs_rs2 = new_offs_rs2;
  68     offs_rs3 = new_offs_rs3;
  69   }
  70
  71   bool sv_check_reg(bool intreg, uint64_t reg);
  72   sv_reg_entry* get_regentry(uint64_t reg, bool isint);
  73   sv_pred_entry* get_predentry(uint64_t reg, bool isint);
  74   reg_t predicate(uint64_t reg, bool isint, bool &zeroing);
  75
  76   void reset_vloop_check(void) { vloop_continue = false; }
  77   bool stop_vloop(void) { return !vloop_continue; }
  78
  79 private:
  80   processor_t *p;
  81   bool vloop_continue;
  82   unsigned int fimap;
  83   uint64_t cached_rd;
  84   uint64_t cached_rs1;
  85   uint64_t cached_rs2;
  86   uint64_t cached_rs3;
  87   int offs_rd;
  88   int offs_rs1;
  89   int offs_rs2;
  90   int offs_rs3;
  91   int new_offs_rd;
  92   int new_offs_rs1;
  93   int new_offs_rs2;
  94   int new_offs_rs3;
  95   uint64_t &prd;
  96   uint64_t &prs1;
  97   uint64_t &prs2;
  98   uint64_t &prs3;
  99
 100   // remaps the register through the lookup table.
 101   // will need to take the current loop index/offset somehow
 102   uint64_t remap(uint64_t reg, bool isint, int &offs, int &newoffs);
 103
 104   // cached version of remap: if remap is called multiple times
 105   // by an emulated instruction it would increment the loop offset
 106   // before it's supposed to.
 107   uint64_t _remap(uint64_t reg, bool isint, int &offs,
 108                   uint64_t &cached, int &newoffs)
 109   {
 110     if (cached == 0xff)
 111     {
 112         cached = remap(reg, isint, offs, newoffs);
 113     }
 114     else
 115     {
 116         if (sv_check_reg(isint, reg))
 117         {
 118             vloop_continue = true;
 119         }
 120     }
 121     return cached;
 122   }
 123
 124   uint64_t predicated(uint64_t reg, int offs, uint64_t pred);
 125 };
 126
 127 #endif