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[riscv-isa-sim.git] / riscv / sv_mmu.h
1 #ifndef _SV_MMU_H
2 #define _SV_MMU_H
3
4 #include "mmu.h"
5 #include "processor.h"
6
7 //typedef reg_t sv_reg_t;
8 //typedef sreg_t sv_sreg_t;
9
10 class sv_mmu_t : public mmu_t
11 {
12 public:
13 sv_mmu_t(simif_t* sim, processor_t* proc) : mmu_t(sim, proc) {}
14
15 #define sv_load_func_decl(type) \
16 sv_reg_t load_##type(reg_spec_t const& reg, sv_reg_t const& offs); \
17 sv_reg_t load_##type(reg_t const& addr);
18
19 // load value from memory at aligned address; zero extend to register width
20 sv_load_func_decl(uint8)
21 sv_load_func_decl(uint16)
22 sv_load_func_decl(uint32)
23 sv_load_func_decl(uint64)
24
25 // load value from memory at aligned address; sign extend to register width
26 sv_load_func_decl(int8)
27 sv_load_func_decl(int16)
28 sv_load_func_decl(int32)
29 sv_load_func_decl(int64)
30
31 #define sv_store_func_decl(type) \
32 void store_##type(reg_spec_t const& reg, sv_reg_t const& offs, \
33 type##_t val); \
34 void store_##type(sv_reg_t const& addr, type##_t val);
35
36 // store value to memory at aligned address
37 sv_store_func_decl(uint8)
38 sv_store_func_decl(uint16)
39 sv_store_func_decl(uint32)
40 sv_store_func_decl(uint64)
41
42 #define sv_amo_func(type) \
43 template<typename _op> \
44 sv_reg_t amo_##type(sv_reg_t const& addr, sv_reg_t const& rhs, _op f) { \
45 type##_t v = mmu_t::amo_##type(addr, rhs, f); \
46 return sv_reg_t(v); \
47 }
48
49 sv_amo_func(uint32)
50 sv_amo_func(uint64)
51
52 void store_float128(sv_reg_t const& addr, float128_t val);
53 sv_float128_t load_float128(sv_reg_t const& addr);
54
55 void acquire_load_reservation(sv_reg_t const& vaddr);
56 bool check_load_reservation(sv_reg_t const& vaddr);
57
58 };
59
60 #endif