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HEAD
Add support for virtual priv register. (#59)
[riscv-isa-sim.git]
/
rvc
/
insns
/
c_lw.h
1
require_rvc
;
2
CRDS
=
mmu
.
load_int32
(
CRS1S
+
CIMM5
*
4
);
projects / riscv-isa-sim.git / blob