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HEAD
Add support for virtual priv register. (#59)
[riscv-isa-sim.git]
/
rvc
/
insns
/
c_swsp.h
1
require_rvc
;
2
mmu
.
store_uint32
(
XPR
[
30
]+
CIMM6
*
4
,
CRS2
);
projects / riscv-isa-sim.git / blob