1 // See LICENSE for license details.
10 struct : public arg_t
{
11 std::string
to_string(insn_t insn
) const {
12 return std::to_string((int)insn
.i_imm()) + '(' + xpr_name
[insn
.rs1()] + ')';
16 struct : public arg_t
{
17 std::string
to_string(insn_t insn
) const {
18 return std::to_string((int)insn
.s_imm()) + '(' + xpr_name
[insn
.rs1()] + ')';
22 struct : public arg_t
{
23 std::string
to_string(insn_t insn
) const {
24 return std::string("(") + xpr_name
[insn
.rs1()] + ')';
28 struct : public arg_t
{
29 std::string
to_string(insn_t insn
) const {
30 return xpr_name
[insn
.rd()];
34 struct : public arg_t
{
35 std::string
to_string(insn_t insn
) const {
36 return xpr_name
[insn
.rs1()];
40 struct : public arg_t
{
41 std::string
to_string(insn_t insn
) const {
42 return xpr_name
[insn
.rs2()];
46 struct : public arg_t
{
47 std::string
to_string(insn_t insn
) const {
48 return fpr_name
[insn
.rd()];
52 struct : public arg_t
{
53 std::string
to_string(insn_t insn
) const {
54 return fpr_name
[insn
.rs1()];
58 struct : public arg_t
{
59 std::string
to_string(insn_t insn
) const {
60 return fpr_name
[insn
.rs2()];
64 struct : public arg_t
{
65 std::string
to_string(insn_t insn
) const {
66 return fpr_name
[insn
.rs3()];
70 struct : public arg_t
{
71 std::string
to_string(insn_t insn
) const {
74 #define DECLARE_CSR(name, num) case num: return #name;
80 snprintf(buf
, sizeof buf
, "unknown_%03" PRIx64
, insn
.csr());
81 return std::string(buf
);
87 struct : public arg_t
{
88 std::string
to_string(insn_t insn
) const {
89 return std::to_string((int)insn
.i_imm());
93 struct : public arg_t
{
94 std::string
to_string(insn_t insn
) const {
95 return std::to_string((int)insn
.shamt());
99 struct : public arg_t
{
100 std::string
to_string(insn_t insn
) const {
102 s
<< std::hex
<< "0x" << ((uint32_t)insn
.u_imm() >> 12);
107 struct : public arg_t
{
108 std::string
to_string(insn_t insn
) const {
109 return std::to_string(insn
.rs1());
113 struct : public arg_t
{
114 std::string
to_string(insn_t insn
) const {
116 int32_t target
= insn
.sb_imm();
117 char sign
= target
>= 0 ? '+' : '-';
118 s
<< "pc " << sign
<< ' ' << abs(target
);
123 struct : public arg_t
{
124 std::string
to_string(insn_t insn
) const {
126 int32_t target
= insn
.uj_imm();
127 char sign
= target
>= 0 ? '+' : '-';
128 s
<< "pc " << sign
<< std::hex
<< " 0x" << abs(target
);
133 struct : public arg_t
{
134 std::string
to_string(insn_t insn
) const {
135 return xpr_name
[insn
.rvc_rs1()];
139 struct : public arg_t
{
140 std::string
to_string(insn_t insn
) const {
141 return xpr_name
[insn
.rvc_rs2()];
145 struct : public arg_t
{
146 std::string
to_string(insn_t insn
) const {
147 return fpr_name
[insn
.rvc_rs2()];
151 struct : public arg_t
{
152 std::string
to_string(insn_t insn
) const {
153 return xpr_name
[insn
.rvc_rs1s()];
157 struct : public arg_t
{
158 std::string
to_string(insn_t insn
) const {
159 return xpr_name
[insn
.rvc_rs2s()];
163 struct : public arg_t
{
164 std::string
to_string(insn_t insn
) const {
165 return fpr_name
[insn
.rvc_rs2s()];
169 struct : public arg_t
{
170 std::string
to_string(insn_t insn
) const {
171 return xpr_name
[X_SP
];
175 struct : public arg_t
{
176 std::string
to_string(insn_t insn
) const {
177 return std::to_string((int)insn
.rvc_imm());
181 struct : public arg_t
{
182 std::string
to_string(insn_t insn
) const {
183 return std::to_string((int)insn
.rvc_addi4spn_imm());
187 struct : public arg_t
{
188 std::string
to_string(insn_t insn
) const {
189 return std::to_string((int)insn
.rvc_addi16sp_imm());
193 struct : public arg_t
{
194 std::string
to_string(insn_t insn
) const {
195 return std::to_string((int)insn
.rvc_lwsp_imm());
199 struct : public arg_t
{
200 std::string
to_string(insn_t insn
) const {
201 return std::to_string((int)(insn
.rvc_imm() & 0x3f));
205 struct : public arg_t
{
206 std::string
to_string(insn_t insn
) const {
208 s
<< std::hex
<< "0x" << ((uint32_t)insn
.rvc_imm() << 12 >> 12);
213 struct : public arg_t
{
214 std::string
to_string(insn_t insn
) const {
215 return std::to_string((int)insn
.rvc_lwsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
219 struct : public arg_t
{
220 std::string
to_string(insn_t insn
) const {
221 return std::to_string((int)insn
.rvc_ldsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
225 struct : public arg_t
{
226 std::string
to_string(insn_t insn
) const {
227 return std::to_string((int)insn
.rvc_swsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
231 struct : public arg_t
{
232 std::string
to_string(insn_t insn
) const {
233 return std::to_string((int)insn
.rvc_sdsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
237 struct : public arg_t
{
238 std::string
to_string(insn_t insn
) const {
239 return std::to_string((int)insn
.rvc_lw_imm()) + '(' + xpr_name
[insn
.rvc_rs1s()] + ')';
243 struct : public arg_t
{
244 std::string
to_string(insn_t insn
) const {
245 return std::to_string((int)insn
.rvc_ld_imm()) + '(' + xpr_name
[insn
.rvc_rs1s()] + ')';
249 struct : public arg_t
{
250 std::string
to_string(insn_t insn
) const {
252 int32_t target
= insn
.rvc_b_imm();
253 char sign
= target
>= 0 ? '+' : '-';
254 s
<< "pc " << sign
<< ' ' << abs(target
);
259 struct : public arg_t
{
260 std::string
to_string(insn_t insn
) const {
262 int32_t target
= insn
.rvc_j_imm();
263 char sign
= target
>= 0 ? '+' : '-';
264 s
<< "pc " << sign
<< ' ' << abs(target
);
269 std::string
disassembler_t::disassemble(insn_t insn
) const
271 const disasm_insn_t
* disasm_insn
= lookup(insn
);
272 return disasm_insn
? disasm_insn
->to_string(insn
) : "unknown";
275 disassembler_t::disassembler_t(int xlen
)
277 const uint32_t mask_rd
= 0x1fUL
<< 7;
278 const uint32_t match_rd_ra
= 1UL << 7;
279 const uint32_t mask_rs1
= 0x1fUL
<< 15;
280 const uint32_t match_rs1_ra
= 1UL << 15;
281 const uint32_t mask_rs2
= 0x1fUL
<< 20;
282 const uint32_t mask_imm
= 0xfffUL
<< 20;
283 const uint32_t match_imm_1
= 1UL << 20;
284 const uint32_t mask_rvc_rs2
= 0x1fUL
<< 2;
285 const uint32_t mask_rvc_imm
= mask_rvc_rs2
| 0x1000UL
;
287 #define DECLARE_INSN(code, match, mask) \
288 const uint32_t match_##code = match; \
289 const uint32_t mask_##code = mask;
290 #include "encoding.h"
293 // explicit per-instruction disassembly
294 #define DISASM_INSN(name, code, extra, ...) \
295 add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
296 #define DEFINE_NOARG(code) \
297 add_insn(new disasm_insn_t(#code, match_##code, mask_##code, {}));
298 #define DEFINE_RTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &xrs2})
299 #define DEFINE_ITYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &imm})
300 #define DEFINE_ITYPE_SHIFT(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &shamt})
301 #define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, {&xrd, &imm})
302 #define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, {&xrd, &xrs1})
303 #define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, {&xrs1})
304 #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &bigimm})
305 #define DEFINE_BTYPE(code) DISASM_INSN(#code, code, 0, {&xrs1, &xrs2, &branch_target})
306 #define DEFINE_B0TYPE(name, code) DISASM_INSN(name, code, mask_rs1 | mask_rs2, {&branch_target})
307 #define DEFINE_B1TYPE(name, code) DISASM_INSN(name, code, mask_rs2, {&xrs1, &branch_target})
308 #define DEFINE_XLOAD(code) DISASM_INSN(#code, code, 0, {&xrd, &load_address})
309 #define DEFINE_XSTORE(code) DISASM_INSN(#code, code, 0, {&xrs2, &store_address})
310 #define DEFINE_XAMO(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs2, &amo_address})
311 #define DEFINE_XAMO_LR(code) DISASM_INSN(#code, code, 0, {&xrd, &amo_address})
312 #define DEFINE_FLOAD(code) DISASM_INSN(#code, code, 0, {&frd, &load_address})
313 #define DEFINE_FSTORE(code) DISASM_INSN(#code, code, 0, {&frs2, &store_address})
314 #define DEFINE_FRTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2})
315 #define DEFINE_FR1TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1})
316 #define DEFINE_FR3TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2, &frs3})
317 #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &frs1})
318 #define DEFINE_FX2TYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &frs1, &frs2})
319 #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &xrs1})
320 #define DEFINE_SFENCE_TYPE(code) DISASM_INSN(#code, code, 0, {&xrs1, &xrs2})
335 DEFINE_XAMO(amoadd_w
)
336 DEFINE_XAMO(amoswap_w
)
337 DEFINE_XAMO(amoand_w
)
339 DEFINE_XAMO(amoxor_w
)
340 DEFINE_XAMO(amomin_w
)
341 DEFINE_XAMO(amomax_w
)
342 DEFINE_XAMO(amominu_w
)
343 DEFINE_XAMO(amomaxu_w
)
344 DEFINE_XAMO(amoadd_d
)
345 DEFINE_XAMO(amoswap_d
)
346 DEFINE_XAMO(amoand_d
)
348 DEFINE_XAMO(amoxor_d
)
349 DEFINE_XAMO(amomin_d
)
350 DEFINE_XAMO(amomax_d
)
351 DEFINE_XAMO(amominu_d
)
352 DEFINE_XAMO(amomaxu_d
)
367 add_insn(new disasm_insn_t("j", match_jal
, mask_jal
| mask_rd
, {&jump_target
}));
368 add_insn(new disasm_insn_t("jal", match_jal
| match_rd_ra
, mask_jal
| mask_rd
, {&jump_target
}));
369 add_insn(new disasm_insn_t("jal", match_jal
, mask_jal
, {&xrd
, &jump_target
}));
371 DEFINE_B1TYPE("beqz", beq
);
372 DEFINE_B1TYPE("bnez", bne
);
373 DEFINE_B1TYPE("bltz", blt
);
374 DEFINE_B1TYPE("bgez", bge
);
385 add_insn(new disasm_insn_t("ret", match_jalr
| match_rs1_ra
, mask_jalr
| mask_rd
| mask_rs1
| mask_imm
, {}));
386 DEFINE_I2TYPE("jr", jalr
);
387 add_insn(new disasm_insn_t("jalr", match_jalr
| match_rd_ra
, mask_jalr
| mask_rd
| mask_imm
, {&xrs1
}));
390 add_insn(new disasm_insn_t("nop", match_addi
, mask_addi
| mask_rd
| mask_rs1
| mask_imm
, {}));
391 add_insn(new disasm_insn_t(" - ", match_xor
, mask_xor
| mask_rd
| mask_rs1
| mask_rs2
, {})); // for machine-generated bubbles
392 DEFINE_I0TYPE("li", addi
);
393 DEFINE_I1TYPE("mv", addi
);
396 add_insn(new disasm_insn_t("seqz", match_sltiu
| match_imm_1
, mask_sltiu
| mask_imm
, {&xrd
, &xrs1
}));
398 add_insn(new disasm_insn_t("not", match_xori
| mask_imm
, mask_xori
| mask_imm
, {&xrd
, &xrs1
}));
401 DEFINE_ITYPE_SHIFT(slli
);
402 DEFINE_ITYPE_SHIFT(srli
);
403 DEFINE_ITYPE_SHIFT(srai
);
407 DEFINE_I1TYPE("sext.w", addiw
);
410 DEFINE_ITYPE_SHIFT(slliw
);
411 DEFINE_ITYPE_SHIFT(srliw
);
412 DEFINE_ITYPE_SHIFT(sraiw
);
418 add_insn(new disasm_insn_t("snez", match_sltu
, mask_sltu
| mask_rs1
, {&xrd
, &xrs2
}));
428 DEFINE_RTYPE(mulhsu
);
445 DEFINE_NOARG(ebreak
);
452 DEFINE_NOARG(fence_i
);
453 DEFINE_SFENCE_TYPE(sfence_vma
);
455 add_insn(new disasm_insn_t("csrr", match_csrrs
, mask_csrrs
| mask_rs1
, {&xrd
, &csr
}));
456 add_insn(new disasm_insn_t("csrw", match_csrrw
, mask_csrrw
| mask_rd
, {&csr
, &xrs1
}));
457 add_insn(new disasm_insn_t("csrs", match_csrrs
, mask_csrrs
| mask_rd
, {&csr
, &xrs1
}));
458 add_insn(new disasm_insn_t("csrc", match_csrrc
, mask_csrrc
| mask_rd
, {&csr
, &xrs1
}));
459 add_insn(new disasm_insn_t("csrwi", match_csrrwi
, mask_csrrwi
| mask_rd
, {&csr
, &zimm5
}));
460 add_insn(new disasm_insn_t("csrsi", match_csrrsi
, mask_csrrsi
| mask_rd
, {&csr
, &zimm5
}));
461 add_insn(new disasm_insn_t("csrci", match_csrrci
, mask_csrrci
| mask_rd
, {&csr
, &zimm5
}));
462 add_insn(new disasm_insn_t("csrrw", match_csrrw
, mask_csrrw
, {&xrd
, &csr
, &xrs1
}));
463 add_insn(new disasm_insn_t("csrrs", match_csrrs
, mask_csrrs
, {&xrd
, &csr
, &xrs1
}));
464 add_insn(new disasm_insn_t("csrrc", match_csrrc
, mask_csrrc
, {&xrd
, &csr
, &xrs1
}));
465 add_insn(new disasm_insn_t("csrrwi", match_csrrwi
, mask_csrrwi
, {&xrd
, &csr
, &zimm5
}));
466 add_insn(new disasm_insn_t("csrrsi", match_csrrsi
, mask_csrrsi
, {&xrd
, &csr
, &zimm5
}));
467 add_insn(new disasm_insn_t("csrrci", match_csrrci
, mask_csrrci
, {&xrd
, &csr
, &zimm5
}));
469 DEFINE_FRTYPE(fadd_s
);
470 DEFINE_FRTYPE(fsub_s
);
471 DEFINE_FRTYPE(fmul_s
);
472 DEFINE_FRTYPE(fdiv_s
);
473 DEFINE_FR1TYPE(fsqrt_s
);
474 DEFINE_FRTYPE(fmin_s
);
475 DEFINE_FRTYPE(fmax_s
);
476 DEFINE_FR3TYPE(fmadd_s
);
477 DEFINE_FR3TYPE(fmsub_s
);
478 DEFINE_FR3TYPE(fnmadd_s
);
479 DEFINE_FR3TYPE(fnmsub_s
);
480 DEFINE_FRTYPE(fsgnj_s
);
481 DEFINE_FRTYPE(fsgnjn_s
);
482 DEFINE_FRTYPE(fsgnjx_s
);
483 DEFINE_FR1TYPE(fcvt_s_d
);
484 DEFINE_FR1TYPE(fcvt_s_q
);
485 DEFINE_XFTYPE(fcvt_s_l
);
486 DEFINE_XFTYPE(fcvt_s_lu
);
487 DEFINE_XFTYPE(fcvt_s_w
);
488 DEFINE_XFTYPE(fcvt_s_wu
);
489 DEFINE_XFTYPE(fcvt_s_wu
);
490 DEFINE_XFTYPE(fmv_w_x
);
491 DEFINE_FXTYPE(fcvt_l_s
);
492 DEFINE_FXTYPE(fcvt_lu_s
);
493 DEFINE_FXTYPE(fcvt_w_s
);
494 DEFINE_FXTYPE(fcvt_wu_s
);
495 DEFINE_FXTYPE(fclass_s
);
496 DEFINE_FXTYPE(fmv_x_w
);
497 DEFINE_FX2TYPE(feq_s
);
498 DEFINE_FX2TYPE(flt_s
);
499 DEFINE_FX2TYPE(fle_s
);
501 DEFINE_FRTYPE(fadd_d
);
502 DEFINE_FRTYPE(fsub_d
);
503 DEFINE_FRTYPE(fmul_d
);
504 DEFINE_FRTYPE(fdiv_d
);
505 DEFINE_FR1TYPE(fsqrt_d
);
506 DEFINE_FRTYPE(fmin_d
);
507 DEFINE_FRTYPE(fmax_d
);
508 DEFINE_FR3TYPE(fmadd_d
);
509 DEFINE_FR3TYPE(fmsub_d
);
510 DEFINE_FR3TYPE(fnmadd_d
);
511 DEFINE_FR3TYPE(fnmsub_d
);
512 DEFINE_FRTYPE(fsgnj_d
);
513 DEFINE_FRTYPE(fsgnjn_d
);
514 DEFINE_FRTYPE(fsgnjx_d
);
515 DEFINE_FR1TYPE(fcvt_d_s
);
516 DEFINE_FR1TYPE(fcvt_d_q
);
517 DEFINE_XFTYPE(fcvt_d_l
);
518 DEFINE_XFTYPE(fcvt_d_lu
);
519 DEFINE_XFTYPE(fcvt_d_w
);
520 DEFINE_XFTYPE(fcvt_d_wu
);
521 DEFINE_XFTYPE(fcvt_d_wu
);
522 DEFINE_XFTYPE(fmv_d_x
);
523 DEFINE_FXTYPE(fcvt_l_d
);
524 DEFINE_FXTYPE(fcvt_lu_d
);
525 DEFINE_FXTYPE(fcvt_w_d
);
526 DEFINE_FXTYPE(fcvt_wu_d
);
527 DEFINE_FXTYPE(fclass_d
);
528 DEFINE_FXTYPE(fmv_x_d
);
529 DEFINE_FX2TYPE(feq_d
);
530 DEFINE_FX2TYPE(flt_d
);
531 DEFINE_FX2TYPE(fle_d
);
533 DEFINE_FRTYPE(fadd_q
);
534 DEFINE_FRTYPE(fsub_q
);
535 DEFINE_FRTYPE(fmul_q
);
536 DEFINE_FRTYPE(fdiv_q
);
537 DEFINE_FR1TYPE(fsqrt_q
);
538 DEFINE_FRTYPE(fmin_q
);
539 DEFINE_FRTYPE(fmax_q
);
540 DEFINE_FR3TYPE(fmadd_q
);
541 DEFINE_FR3TYPE(fmsub_q
);
542 DEFINE_FR3TYPE(fnmadd_q
);
543 DEFINE_FR3TYPE(fnmsub_q
);
544 DEFINE_FRTYPE(fsgnj_q
);
545 DEFINE_FRTYPE(fsgnjn_q
);
546 DEFINE_FRTYPE(fsgnjx_q
);
547 DEFINE_FR1TYPE(fcvt_q_s
);
548 DEFINE_FR1TYPE(fcvt_q_d
);
549 DEFINE_XFTYPE(fcvt_q_l
);
550 DEFINE_XFTYPE(fcvt_q_lu
);
551 DEFINE_XFTYPE(fcvt_q_w
);
552 DEFINE_XFTYPE(fcvt_q_wu
);
553 DEFINE_XFTYPE(fcvt_q_wu
);
554 DEFINE_XFTYPE(fmv_q_x
);
555 DEFINE_FXTYPE(fcvt_l_q
);
556 DEFINE_FXTYPE(fcvt_lu_q
);
557 DEFINE_FXTYPE(fcvt_w_q
);
558 DEFINE_FXTYPE(fcvt_wu_q
);
559 DEFINE_FXTYPE(fclass_q
);
560 DEFINE_FXTYPE(fmv_x_q
);
561 DEFINE_FX2TYPE(feq_q
);
562 DEFINE_FX2TYPE(flt_q
);
563 DEFINE_FX2TYPE(fle_q
);
565 DISASM_INSN("c.ebreak", c_add
, mask_rd
| mask_rvc_rs2
, {});
566 add_insn(new disasm_insn_t("ret", match_c_jr
| match_rd_ra
, mask_c_jr
| mask_rd
| mask_rvc_imm
, {}));
567 DISASM_INSN("c.jr", c_jr
, mask_rvc_imm
, {&rvc_rs1
});
568 DISASM_INSN("c.jalr", c_jalr
, mask_rvc_imm
, {&rvc_rs1
});
569 DISASM_INSN("c.nop", c_addi
, mask_rd
| mask_rvc_imm
, {});
570 DISASM_INSN("c.addi16sp", c_addi16sp
, mask_rd
, {&rvc_sp
, &rvc_addi16sp_imm
});
571 DISASM_INSN("c.addi4spn", c_addi4spn
, 0, {&rvc_rs1s
, &rvc_sp
, &rvc_addi4spn_imm
});
572 DISASM_INSN("c.li", c_li
, 0, {&xrd
, &rvc_imm
});
573 DISASM_INSN("c.lui", c_lui
, 0, {&xrd
, &rvc_uimm
});
574 DISASM_INSN("c.addi", c_addi
, 0, {&xrd
, &rvc_imm
});
575 DISASM_INSN("c.slli", c_slli
, 0, {&rvc_rs1
, &rvc_shamt
});
576 DISASM_INSN("c.srli", c_srli
, 0, {&rvc_rs1s
, &rvc_shamt
});
577 DISASM_INSN("c.srai", c_srai
, 0, {&rvc_rs1s
, &rvc_shamt
});
578 DISASM_INSN("c.andi", c_andi
, 0, {&rvc_rs1s
, &rvc_imm
});
579 DISASM_INSN("c.mv", c_mv
, 0, {&xrd
, &rvc_rs2
});
580 DISASM_INSN("c.add", c_add
, 0, {&xrd
, &rvc_rs2
});
581 DISASM_INSN("c.addw", c_addw
, 0, {&rvc_rs1s
, &rvc_rs2s
});
582 DISASM_INSN("c.sub", c_sub
, 0, {&rvc_rs1s
, &rvc_rs2s
});
583 DISASM_INSN("c.subw", c_subw
, 0, {&rvc_rs1s
, &rvc_rs2s
});
584 DISASM_INSN("c.and", c_and
, 0, {&rvc_rs1s
, &rvc_rs2s
});
585 DISASM_INSN("c.or", c_or
, 0, {&rvc_rs1s
, &rvc_rs2s
});
586 DISASM_INSN("c.xor", c_xor
, 0, {&rvc_rs1s
, &rvc_rs2s
});
587 DISASM_INSN("c.lwsp", c_lwsp
, 0, {&xrd
, &rvc_lwsp_address
});
588 DISASM_INSN("c.fld", c_fld
, 0, {&rvc_fp_rs2s
, &rvc_ld_address
});
589 DISASM_INSN("c.swsp", c_swsp
, 0, {&rvc_rs2
, &rvc_swsp_address
});
590 DISASM_INSN("c.lw", c_lw
, 0, {&rvc_rs2s
, &rvc_lw_address
});
591 DISASM_INSN("c.sw", c_sw
, 0, {&rvc_rs2s
, &rvc_lw_address
});
592 DISASM_INSN("c.beqz", c_beqz
, 0, {&rvc_rs1s
, &rvc_branch_target
});
593 DISASM_INSN("c.bnez", c_bnez
, 0, {&rvc_rs1s
, &rvc_branch_target
});
594 DISASM_INSN("c.j", c_j
, 0, {&rvc_jump_target
});
595 DISASM_INSN("c.fldsp", c_fldsp
, 0, {&rvc_fp_rs2s
, &rvc_ldsp_address
});
596 DISASM_INSN("c.fsd", c_fsd
, 0, {&rvc_fp_rs2s
, &rvc_ld_address
});
597 DISASM_INSN("c.fsdsp", c_fsdsp
, 0, {&rvc_fp_rs2s
, &rvc_sdsp_address
});
600 DISASM_INSN("c.flw", c_flw
, 0, {&rvc_fp_rs2s
, &rvc_lw_address
});
601 DISASM_INSN("c.flwsp", c_flwsp
, 0, {&frd
, &rvc_lwsp_address
});
602 DISASM_INSN("c.fsw", c_fsw
, 0, {&rvc_fp_rs2s
, &rvc_lw_address
});
603 DISASM_INSN("c.fswsp", c_fswsp
, 0, {&rvc_fp_rs2
, &rvc_swsp_address
});
604 DISASM_INSN("c.jal", c_jal
, 0, {&rvc_jump_target
});
606 DISASM_INSN("c.ld", c_ld
, 0, {&rvc_rs2s
, &rvc_ld_address
});
607 DISASM_INSN("c.ldsp", c_ldsp
, 0, {&xrd
, &rvc_ldsp_address
});
608 DISASM_INSN("c.sd", c_sd
, 0, {&rvc_rs2s
, &rvc_ld_address
});
609 DISASM_INSN("c.sdsp", c_sdsp
, 0, {&rvc_rs2
, &rvc_sdsp_address
});
610 DISASM_INSN("c.addiw", c_addiw
, 0, {&xrd
, &rvc_imm
});
613 // provide a default disassembly for all instructions as a fallback
614 #define DECLARE_INSN(code, match, mask) \
615 add_insn(new disasm_insn_t(#code " (args unknown)", match, mask, {}));
616 #include "encoding.h"
620 const disasm_insn_t
* disassembler_t::lookup(insn_t insn
) const
622 size_t idx
= insn
.bits() % HASH_SIZE
;
623 for (size_t j
= 0; j
< chain
[idx
].size(); j
++)
624 if(*chain
[idx
][j
] == insn
)
625 return chain
[idx
][j
];
628 for (size_t j
= 0; j
< chain
[idx
].size(); j
++)
629 if(*chain
[idx
][j
] == insn
)
630 return chain
[idx
][j
];
635 void disassembler_t::add_insn(disasm_insn_t
* insn
)
637 size_t idx
= HASH_SIZE
;
638 if (insn
->get_mask() % HASH_SIZE
== HASH_SIZE
- 1)
639 idx
= insn
->get_match() % HASH_SIZE
;
640 chain
[idx
].push_back(insn
);
643 disassembler_t::~disassembler_t()
645 for (size_t i
= 0; i
< HASH_SIZE
+1; i
++)
646 for (size_t j
= 0; j
< chain
[i
].size(); j
++)