src/TLB/ariane/test/test_ptw.py

   1 import sys
   2 sys.path.append("../src")
   3 sys.path.append("../../../TestUtil")
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from TLB.ariane.ptw import PTW, PTE
   8
   9
  10 def testbench(dut):
  11
  12     addr = 0x8000000
  13
  14     #pte = PTE()
  15     #yield pte.v.eq(1)
  16     #yield pte.r.eq(1)
  17
  18     yield dut.req_port_i.data_gnt.eq(1)
  19     yield dut.req_port_i.data_rvalid.eq(1)
  20     yield dut.req_port_i.data_rdata.eq(0x43)#pte.flatten())
  21
  22     # data lookup
  23     yield dut.en_ld_st_translation_i.eq(1)
  24     yield dut.asid_i.eq(1)
  25
  26     yield dut.dtlb_access_i.eq(1)
  27     yield dut.dtlb_hit_i.eq(0)
  28     yield dut.dtlb_vaddr_i.eq(0x400000000)
  29
  30     yield
  31     yield
  32     yield
  33
  34     yield dut.dtlb_access_i.eq(1)
  35     yield dut.dtlb_hit_i.eq(0)
  36     yield dut.dtlb_vaddr_i.eq(0x200000)
  37
  38     yield
  39     yield
  40     yield
  41
  42     yield dut.req_port_i.data_gnt.eq(0)
  43     yield dut.dtlb_access_i.eq(1)
  44     yield dut.dtlb_hit_i.eq(0)
  45     yield dut.dtlb_vaddr_i.eq(0x400000011)
  46
  47     yield
  48     yield dut.req_port_i.data_gnt.eq(1)
  49     yield
  50     yield
  51
  52     # data lookup, PTW levels 1-2-3
  53     addr = 0x4000000
  54     yield dut.dtlb_vaddr_i.eq(addr)
  55     yield dut.mxr_i.eq(0x1)
  56     yield dut.req_port_i.data_gnt.eq(1)
  57     yield dut.req_port_i.data_rvalid.eq(1)
  58     yield dut.req_port_i.data_rdata.eq(0x41 | (addr>>12)<<10)#pte.flatten())
  59
  60     yield dut.en_ld_st_translation_i.eq(1)
  61     yield dut.asid_i.eq(1)
  62
  63     yield dut.dtlb_access_i.eq(1)
  64     yield dut.dtlb_hit_i.eq(0)
  65     yield dut.dtlb_vaddr_i.eq(addr)
  66
  67     yield
  68     yield
  69     yield
  70     yield
  71     yield
  72     yield
  73     yield
  74     yield
  75
  76     yield dut.req_port_i.data_gnt.eq(0)
  77     yield dut.dtlb_access_i.eq(1)
  78     yield dut.dtlb_hit_i.eq(0)
  79     yield dut.dtlb_vaddr_i.eq(0x400000011)
  80
  81     yield
  82     yield dut.req_port_i.data_gnt.eq(1)
  83     yield
  84     yield
  85     yield
  86     yield
  87
  88
  89     # instruction lookup
  90     yield dut.en_ld_st_translation_i.eq(0)
  91     yield dut.enable_translation_i.eq(1)
  92     yield dut.asid_i.eq(1)
  93
  94     yield dut.itlb_access_i.eq(1)
  95     yield dut.itlb_hit_i.eq(0)
  96     yield dut.itlb_vaddr_i.eq(0x800000)
  97
  98     yield
  99     yield
 100     yield
 101
 102     yield dut.itlb_access_i.eq(1)
 103     yield dut.itlb_hit_i.eq(0)
 104     yield dut.itlb_vaddr_i.eq(0x200000)
 105
 106     yield
 107     yield
 108     yield
 109
 110     yield dut.req_port_i.data_gnt.eq(0)
 111     yield dut.itlb_access_i.eq(1)
 112     yield dut.itlb_hit_i.eq(0)
 113     yield dut.itlb_vaddr_i.eq(0x800011)
 114
 115     yield
 116     yield dut.req_port_i.data_gnt.eq(1)
 117     yield
 118     yield
 119
 120     yield
 121
 122
 123
 124 if __name__ == "__main__":
 125     dut = PTW()
 126     run_simulation(dut, testbench(dut), vcd_name="test_ptw.vcd")
 127     print("PTW Unit Test Success")