src/decoder/test/test_power_major_decoder.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import sys
   6 import unittest
   7 sys.path.append("../")
   8 from power_major_decoder import (PowerMajorDecoder, Function,
   9                                  In1Sel, In2Sel, In3Sel, OutSel,
  10                                  single_bit_flags, get_signal_name,
  11                                  InternalOp, major_opcodes)
  12
  13
  14 class DecoderTestCase(FHDLTestCase):
  15     def test_function_unit(self):
  16         m = Module()
  17         comb = m.d.comb
  18         opcode = Signal(6)
  19         function_unit = Signal(Function)
  20         internal_op = Signal(InternalOp)
  21         in1_sel = Signal(In1Sel)
  22         in2_sel = Signal(In2Sel)
  23         in3_sel = Signal(In3Sel)
  24         out_sel = Signal(OutSel)
  25
  26         m.submodules.dut = dut = PowerMajorDecoder()
  27         comb += [dut.opcode_in.eq(opcode),
  28                  function_unit.eq(dut.function_unit),
  29                  in1_sel.eq(dut.in1_sel),
  30                  in2_sel.eq(dut.in2_sel),
  31                  in3_sel.eq(dut.in3_sel),
  32                  out_sel.eq(dut.out_sel),
  33                  internal_op.eq(dut.internal_op)]
  34
  35         sim = Simulator(m)
  36
  37         def process():
  38             for row in major_opcodes:
  39                 yield opcode.eq(int(row['opcode']))
  40                 yield Delay(1e-6)
  41                 result = yield function_unit
  42                 expected = Function[row['unit']].value
  43                 self.assertEqual(expected, result)
  44
  45                 result = yield internal_op
  46                 expected = InternalOp[row['internal op']].value
  47                 self.assertEqual(expected, result)
  48
  49                 result = yield in1_sel
  50                 expected = In1Sel[row['in1']].value
  51                 self.assertEqual(expected, result)
  52
  53                 result = yield in2_sel
  54                 expected = In2Sel[row['in2']].value
  55                 self.assertEqual(expected, result)
  56
  57                 result = yield in3_sel
  58                 expected = In3Sel[row['in3']].value
  59                 self.assertEqual(expected, result)
  60
  61                 result = yield out_sel
  62                 expected = OutSel[row['out']].value
  63                 self.assertEqual(expected, result)
  64
  65                 for bit in single_bit_flags:
  66                     sig = getattr(dut, get_signal_name(bit))
  67                     result = yield sig
  68                     expected = int(row[bit])
  69                     self.assertEqual(expected, result)
  70         sim.add_process(process)
  71         with sim.write_vcd("test.vcd", "test.gtkw", traces=[
  72                 opcode, function_unit, internal_op,
  73                 in1_sel, in2_sel]):
  74             sim.run()
  75
  76     def test_ilang(self):
  77         dut = PowerMajorDecoder()
  78         vl = rtlil.convert(dut, ports=dut.ports())
  79         with open("power_major_decoder.il", "w") as f:
  80             f.write(vl)
  81
  82
  83 if __name__ == "__main__":
  84     unittest.main()