1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.test
.utils
import FHDLTestCase
4 from nmigen
.cli
import rtlil
9 from power_decoder
import (create_pdecode
)
10 from power_enums
import (Function
, InternalOp
, In1Sel
, In2Sel
, In3Sel
,
11 OutSel
, RC
, LdstLen
, CryIn
, single_bit_flags
,
12 get_signal_name
, get_csv
)
15 class DecoderTestCase(FHDLTestCase
):
17 def run_tst(self
, bitsel
, csvname
, minor
=None, suffix
=None, opint
=True):
21 function_unit
= Signal(Function
)
22 internal_op
= Signal(InternalOp
)
23 in1_sel
= Signal(In1Sel
)
24 in2_sel
= Signal(In2Sel
)
25 in3_sel
= Signal(In3Sel
)
26 out_sel
= Signal(OutSel
)
28 ldst_len
= Signal(LdstLen
)
29 cry_in
= Signal(CryIn
)
31 # opcodes = get_csv(csvname)
32 m
.submodules
.dut
= dut
= create_pdecode()
33 comb
+= [dut
.opcode_in
.eq(opcode
),
34 function_unit
.eq(dut
.op
.function_unit
),
35 in1_sel
.eq(dut
.op
.in1_sel
),
36 in2_sel
.eq(dut
.op
.in2_sel
),
37 in3_sel
.eq(dut
.op
.in3_sel
),
38 out_sel
.eq(dut
.op
.out_sel
),
39 rc_sel
.eq(dut
.op
.rc_sel
),
40 ldst_len
.eq(dut
.op
.ldst_len
),
41 cry_in
.eq(dut
.op
.cry_in
),
42 internal_op
.eq(dut
.op
.internal_op
)]
45 opcodes
= get_csv(csvname
)
52 if not opint
: # HACK: convert 001---10 to 0b00100010
53 op
= "0b" + op
.replace('-', '0')
54 print ("opint", opint
, row
['opcode'], op
)
57 yield opcode
[bitsel
[0]:bitsel
[1]].eq(int(op
, 0))
61 yield opcode
[minorbits
[0]:minorbits
[1]].eq(minor
[0])
63 # OR 0, 0, 0 ; 0x60000000 is decoded as a NOP
64 # If we're testing the OR instruction, make sure
65 # that the instruction is not 0x60000000
67 yield opcode
[24:25].eq(0b11)
70 signals
= [(function_unit
, Function
, 'unit'),
71 (internal_op
, InternalOp
, 'internal op'),
72 (in1_sel
, In1Sel
, 'in1'),
73 (in2_sel
, In2Sel
, 'in2'),
74 (in3_sel
, In3Sel
, 'in3'),
75 (out_sel
, OutSel
, 'out'),
77 (cry_in
, CryIn
, 'cry in'),
78 (ldst_len
, LdstLen
, 'ldst len')]
79 for sig
, enm
, name
in signals
:
81 expected
= enm
[row
[name
]]
82 msg
= f
"{sig.name} == {enm(result)}, expected: {expected}"
83 self
.assertEqual(enm(result
), expected
, msg
)
84 for bit
in single_bit_flags
:
85 sig
= getattr(dut
.op
, get_signal_name(bit
))
87 expected
= int(row
[bit
])
88 msg
= f
"{sig.name} == {result}, expected: {expected}"
89 self
.assertEqual(expected
, result
, msg
)
90 sim
.add_process(process
)
91 prefix
= os
.path
.splitext(csvname
)[0]
92 with sim
.write_vcd("%s.vcd" % prefix
, "%s.gtkw" % prefix
, traces
=[
93 opcode
, function_unit
, internal_op
,
97 def generate_ilang(self
):
98 pdecode
= create_pdecode()
99 vl
= rtlil
.convert(pdecode
, ports
=pdecode
.ports())
100 with
open("decoder.il", "w") as f
:
103 def test_major(self
):
104 self
.run_tst((26, 32), "major.csv")
105 self
.generate_ilang()
107 def test_minor_19(self
):
108 self
.run_tst((1, 11), "minor_19.csv", minor
=(19, (26, 32)),
111 # def test_minor_19_00000(self):
112 # self.run_tst((1, 11), "minor_19_00000.csv")
114 def test_minor_30(self
):
115 self
.run_tst((1, 5), "minor_30.csv", minor
=(30, (26, 32)))
117 def test_minor_31(self
):
118 self
.run_tst((1, 11), "minor_31.csv", minor
=(31, (26, 32)))
120 def test_minor_58(self
):
121 self
.run_tst((0, 2), "minor_58.csv", minor
=(58, (26, 32)))
123 def test_minor_62(self
):
124 self
.run_tst((0, 2), "minor_62.csv", minor
=(62, (26, 32)))
127 # #def test_minor_31_prefix(self):
128 # # self.run_tst(10, "minor_31.csv", suffix=(5, 10))
130 # def test_extra(self):
131 # self.run_tst(32, "extra.csv", opint=False)
132 # self.generate_ilang(32, "extra.csv", opint=False)
135 if __name__
== "__main__":