src/soc/decoder/test/test_power_decoder.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import os
   6 import unittest
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_enums import (Function, InternalOp,
   9                                      In1Sel, In2Sel, In3Sel,
  10                                      CRInSel, CROutSel,
  11                                      OutSel, RC, LdstLen, CryIn,
  12                                      single_bit_flags,
  13                                      get_signal_name, get_csv)
  14
  15
  16 class DecoderTestCase(FHDLTestCase):
  17
  18     def run_tst(self, bitsel, csvname, minor=None, suffix=None, opint=True):
  19         m = Module()
  20         comb = m.d.comb
  21         opcode = Signal(32)
  22         function_unit = Signal(Function)
  23         internal_op = Signal(InternalOp)
  24         in1_sel = Signal(In1Sel)
  25         in2_sel = Signal(In2Sel)
  26         in3_sel = Signal(In3Sel)
  27         out_sel = Signal(OutSel)
  28         cr_in = Signal(CRInSel)
  29         rc_sel = Signal(RC)
  30         ldst_len = Signal(LdstLen)
  31         cry_in = Signal(CryIn)
  32         bigendian = Signal()
  33         comb += bigendian.eq(1)
  34
  35         # opcodes = get_csv(csvname)
  36         m.submodules.dut = dut = create_pdecode()
  37         comb += [dut.raw_opcode_in.eq(opcode),
  38                  dut.bigendian.eq(bigendian),
  39                  function_unit.eq(dut.op.function_unit),
  40                  in1_sel.eq(dut.op.in1_sel),
  41                  in2_sel.eq(dut.op.in2_sel),
  42                  in3_sel.eq(dut.op.in3_sel),
  43                  out_sel.eq(dut.op.out_sel),
  44                  cr_in.eq(dut.op.cr_in),
  45                  rc_sel.eq(dut.op.rc_sel),
  46                  ldst_len.eq(dut.op.ldst_len),
  47                  cry_in.eq(dut.op.cry_in),
  48                  internal_op.eq(dut.op.internal_op)]
  49
  50         sim = Simulator(m)
  51         opcodes = get_csv(csvname)
  52
  53         def process():
  54             for row in opcodes:
  55                 if not row['unit']:
  56                     continue
  57                 op = row['opcode']
  58                 if not opint: # HACK: convert 001---10 to 0b00100010
  59                     op = "0b" + op.replace('-', '0')
  60                 print ("opint", opint, row['opcode'], op)
  61                 print(row)
  62                 yield opcode.eq(0)
  63                 yield opcode[bitsel[0]:bitsel[1]].eq(int(op, 0))
  64                 if minor:
  65                     print(minor)
  66                     minorbits = minor[1]
  67                     yield opcode[minorbits[0]:minorbits[1]].eq(minor[0])
  68                 else:
  69                     # OR 0, 0, 0  ; 0x60000000 is decoded as a NOP
  70                     # If we're testing the OR instruction, make sure
  71                     # that the instruction is not 0x60000000
  72                     if int(op, 0) == 24:
  73                         yield opcode[24:25].eq(0b11)
  74
  75                 yield Delay(1e-6)
  76                 signals = [(function_unit, Function, 'unit'),
  77                            (internal_op, InternalOp, 'internal op'),
  78                            (in1_sel, In1Sel, 'in1'),
  79                            (in2_sel, In2Sel, 'in2'),
  80                            (in3_sel, In3Sel, 'in3'),
  81                            (out_sel, OutSel, 'out'),
  82                            (cr_in, CRInSel, 'CR in'),
  83                            (rc_sel, RC, 'rc'),
  84                            (cry_in, CryIn, 'cry in'),
  85                            (ldst_len, LdstLen, 'ldst len')]
  86                 for sig, enm, name in signals:
  87                     result = yield sig
  88                     expected = enm[row[name]]
  89                     msg = f"{sig.name} == {enm(result)}, expected: {expected}"
  90                     self.assertEqual(enm(result), expected, msg)
  91                 for bit in single_bit_flags:
  92                     sig = getattr(dut.op, get_signal_name(bit))
  93                     result = yield sig
  94                     expected = int(row[bit])
  95                     msg = f"{sig.name} == {result}, expected: {expected}"
  96                     self.assertEqual(expected, result, msg)
  97         sim.add_process(process)
  98         prefix = os.path.splitext(csvname)[0]
  99         with sim.write_vcd("%s.vcd" % prefix, "%s.gtkw" % prefix, traces=[
 100                 opcode, function_unit, internal_op,
 101                 in1_sel, in2_sel]):
 102             sim.run()
 103
 104     def generate_ilang(self):
 105         pdecode = create_pdecode()
 106         vl = rtlil.convert(pdecode, ports=pdecode.ports())
 107         with open("decoder.il", "w") as f:
 108             f.write(vl)
 109
 110     def test_major(self):
 111         self.run_tst((26, 32), "major.csv")
 112         self.generate_ilang()
 113
 114     def test_minor_19(self):
 115         self.run_tst((1, 11), "minor_19.csv", minor=(19, (26, 32)),
 116                      suffix=(0, 5))
 117
 118     # def test_minor_19_00000(self):
 119     #     self.run_tst((1, 11), "minor_19_00000.csv")
 120
 121     def test_minor_30(self):
 122         self.run_tst((1, 5), "minor_30.csv", minor=(30, (26, 32)))
 123
 124     def test_minor_31(self):
 125         self.run_tst((1, 11), "minor_31.csv", minor=(31, (26, 32)))
 126
 127     def test_minor_58(self):
 128         self.run_tst((0, 2), "minor_58.csv", minor=(58, (26, 32)))
 129
 130     def test_minor_62(self):
 131         self.run_tst((0, 2), "minor_62.csv", minor=(62, (26, 32)))
 132
 133
 134     # #def test_minor_31_prefix(self):
 135     # #    self.run_tst(10, "minor_31.csv", suffix=(5, 10))
 136
 137     # def test_extra(self):
 138     #     self.run_tst(32, "extra.csv", opint=False)
 139     #     self.generate_ilang(32, "extra.csv", opint=False)
 140
 141
 142 if __name__ == "__main__":
 143     unittest.main()