src/soc/experiment/cache_ram.py

   1 # TODO: replace with Memory at some point
   2 from nmigen import Elaboratable, Signal, Array, Module
   3 from nmutil.util import Display
   4
   5 class CacheRam(Elaboratable):
   6
   7     def __init__(self, ROW_BITS=16, WIDTH = 64, TRACE=True, ADD_BUF=False,
   8                        ram_num=0):
   9         self.ram_num = ram_num # for debug reporting
  10         self.ROW_BITS = ROW_BITS
  11         self.WIDTH = WIDTH
  12         self.TRACE = TRACE
  13         self.ADD_BUF = ADD_BUF
  14         self.rd_en     = Signal()
  15         self.rd_addr   = Signal(ROW_BITS)
  16         self.rd_data_o = Signal(WIDTH)
  17         self.wr_sel    = Signal(WIDTH//8)
  18         self.wr_addr   = Signal(ROW_BITS)
  19         self.wr_data   = Signal(WIDTH)
  20
  21     def elaborate(self, platform):
  22         m = Module()
  23         comb, sync = m.d.comb, m.d.sync
  24
  25         ROW_BITS = self.ROW_BITS
  26         WIDTH = self.WIDTH
  27         TRACE = self.TRACE
  28         ADD_BUF = self.ADD_BUF
  29         SIZE = 2**ROW_BITS
  30
  31         ram = Array(Signal(WIDTH) for i in range(SIZE))
  32         #attribute ram_style of ram : signal is "block";
  33
  34         rd_data0 = Signal(WIDTH)
  35
  36         with m.If(TRACE):
  37             with m.If(self.wr_sel.bool()):
  38                 sync += Display( "write ramno %d a: %%x "
  39                                  "sel: %%x dat: %%x" % self.ram_num,
  40                                 self.wr_addr,
  41                                 self.wr_sel, self.wr_data)
  42         for i in range(WIDTH//8):
  43             lbit = i * 8;
  44             mbit = lbit + 8;
  45             with m.If(self.wr_sel[i]):
  46                 sync += ram[self.wr_addr][lbit:mbit].eq(self.wr_data[lbit:mbit])
  47         with m.If(self.rd_en):
  48             sync += rd_data0.eq(ram[self.rd_addr])
  49             if TRACE:
  50                 sync += Display("read ramno %d a: %%x dat: %%x" % self.ram_num,
  51                                 self.rd_addr, ram[self.rd_addr])
  52                 pass
  53
  54
  55         if ADD_BUF:
  56             sync += self.rd_data_o.eq(rd_data0)
  57         else:
  58             comb += self.rd_data_o.eq(rd_data0)
  59
  60         return m