src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=465 - exception handling
  16
  17 """
  18
  19 from nmigen.compat.sim import run_simulation, Settle
  20 from nmigen.cli import rtlil
  21 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  22 from nmutil.iocontrol import RecordObject
  23 from nmigen.utils import log2_int
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from nmutil.util import rising_edge
  27 from openpower.decoder.power_decoder2 import Data
  28 from openpower.decoder.power_enums import MSRSpec
  29 from soc.scoreboard.addr_match import LenExpand
  30 from soc.experiment.mem_types import LDSTException
  31
  32 # for testing purposes
  33 from soc.experiment.testmem import TestMemory
  34 #from soc.scoreboard.addr_split import LDSTSplitter
  35 from nmutil.util import Display
  36
  37 import unittest
  38
  39
  40 class PortInterface(RecordObject):
  41     """PortInterface
  42
  43     defines the interface - the API - that the LDSTCompUnit connects
  44     to.  note that this is NOT a "fire-and-forget" interface.  the
  45     LDSTCompUnit *must* be kept appraised that the request is in
  46     progress, and only when it has a 100% successful completion
  47     can the notification be given (busy dropped).
  48
  49     The interface FSM rules are as follows:
  50
  51     * if busy_o is asserted, a LD/ST is in progress.  further
  52       requests may not be made until busy_o is deasserted.
  53
  54     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  55       will immediately be asserted and remain asserted.
  56
  57     * addr.ok is to be asserted when the LD/ST address is known.
  58       addr.data is to be valid on the same cycle.
  59
  60       addr.ok and addr.data must REMAIN asserted until busy_o
  61       is de-asserted.  this ensures that there is no need
  62       for the L0 Cache/Buffer to have an additional address latch
  63       (because the LDSTCompUnit already has it)
  64
  65     * addr_ok_o (or exception.happened) must be waited for.  these will
  66       be asserted *only* for one cycle and one cycle only.
  67
  68     * exception.happened will be asserted if there is no chance that the
  69       memory request may be fulfilled.
  70
  71       busy_o is deasserted on the same cycle as exception.happened is asserted.
  72
  73     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  74       HUNDRED PERCENT guarantee that the memory request will be
  75       fulfilled.
  76
  77     * for a LD, ld.ok will be asserted - for only one clock cycle -
  78       at any point in the future that is acceptable to the underlying
  79       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  80
  81       busy_o is deasserted on the same cycle as ld.ok is asserted.
  82
  83     * for a ST, st.ok may be asserted only after addr_ok_o had been
  84       asserted, alongside valid st.data at the same time.  st.ok
  85       must only be asserted for one cycle.
  86
  87       the underlying Memory is REQUIRED to pick up that data and
  88       guarantee its delivery.  no back-acknowledgement is required.
  89
  90       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  91     """
  92
  93     def __init__(self, name=None, regwid=64, addrwid=64):
  94
  95         self._regwid = regwid
  96         self._addrwid = addrwid
  97
  98         RecordObject.__init__(self, name=name)
  99
 100         # distinguish op type (ld/st/dcbz)
 101         self.is_ld_i    = Signal(reset_less=True)
 102         self.is_st_i    = Signal(reset_less=True)
 103         self.is_dcbz_i     = Signal(reset_less=True) # cache-line zeroing
 104
 105         # LD/ST data length (TODO: other things may be needed)
 106         self.data_len = Signal(4, reset_less=True)
 107
 108         # atomic reservation (LR/SC - ldarx / stdcx etc.)
 109         self.reserve = Signal(reset_less=True)
 110
 111         # common signals
 112         self.busy_o = Signal(reset_less=True)     # do not use if busy
 113         self.go_die_i = Signal(reset_less=True)   # back to reset
 114         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 115         # addr is valid (TLB, L1 etc.)
 116         self.addr_ok_o = Signal(reset_less=True)
 117         self.exc_o = LDSTException("exc")
 118
 119         # LD/ST
 120         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 121         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 122
 123         # additional "modes"
 124         self.is_nc         = Signal()  # no cacheing
 125
 126         #only priv_mode = not msr_pr is used currently
 127         # TODO: connect signals
 128         self.virt_mode  = Signal() # ctrl.msr(MSR_DR);
 129         self.priv_mode  = Signal() # not ctrl.msr(MSR_PR);
 130         self.mode_32bit = Signal() # not ctrl.msr(MSR_SF);
 131
 132         # mmu
 133         self.mmu_done          = Signal() # keep for now
 134
 135         # dcache
 136         self.ldst_error        = Signal()
 137         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
 138         self.cache_paradox     = Signal()
 139
 140     def connect_port(self, inport):
 141         print("connect_port", self, inport)
 142         return [self.is_ld_i.eq(inport.is_ld_i),
 143                 self.is_st_i.eq(inport.is_st_i),
 144                 self.is_nc.eq(inport.is_nc),
 145                 self.is_dcbz_i.eq(inport.is_dcbz_i),
 146                 self.data_len.eq(inport.data_len),
 147                 self.reserve.eq(inport.reserve),
 148                 self.go_die_i.eq(inport.go_die_i),
 149                 self.addr.data.eq(inport.addr.data),
 150                 self.addr.ok.eq(inport.addr.ok),
 151                 self.st.eq(inport.st),
 152                 self.virt_mode.eq(inport.virt_mode),
 153                 self.priv_mode.eq(inport.priv_mode),
 154                 self.mode_32bit.eq(inport.mode_32bit),
 155                 inport.ld.eq(self.ld),
 156                 inport.busy_o.eq(self.busy_o),
 157                 inport.addr_ok_o.eq(self.addr_ok_o),
 158                 inport.exc_o.eq(self.exc_o),
 159                 inport.mmu_done.eq(self.mmu_done),
 160                 inport.ldst_error.eq(self.ldst_error),
 161                 inport.cache_paradox.eq(self.cache_paradox)
 162                 ]
 163
 164
 165 class PortInterfaceBase(Elaboratable):
 166     """PortInterfaceBase
 167
 168     Base class for PortInterface-compliant Memory read/writers
 169     """
 170
 171     def __init__(self, regwid=64, addrwid=4):
 172         self.regwid = regwid
 173         self.addrwid = addrwid
 174         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 175
 176     @property
 177     def addrbits(self):
 178         return log2_int(self.regwid//8)
 179
 180     def splitaddr(self, addr):
 181         """split the address into top and bottom bits of the memory granularity
 182         """
 183         return addr[:self.addrbits], addr[self.addrbits:]
 184
 185     def connect_port(self, inport):
 186         return self.pi.connect_port(inport)
 187
 188     def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz): pass
 189     def set_rd_addr(self, m, addr, mask, misalign, msr): pass
 190     def set_wr_data(self, m, data, wen): pass
 191     def get_rd_data(self, m): pass
 192
 193     def elaborate(self, platform):
 194         m = Module()
 195         comb, sync = m.d.comb, m.d.sync
 196
 197         # state-machine latches
 198         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 199         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 200         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 201         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 202         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 203         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 204         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 205
 206         self.busy_l = busy_l
 207
 208         sync += st_done.s.eq(0)
 209         comb += st_done.r.eq(0)
 210         comb += st_active.r.eq(0)
 211         comb += ld_active.r.eq(0)
 212         comb += cyc_l.s.eq(0)
 213         comb += cyc_l.r.eq(0)
 214         comb += busy_l.s.eq(0)
 215         comb += busy_l.r.eq(0)
 216         sync += adrok_l.s.eq(0)
 217         comb += adrok_l.r.eq(0)
 218
 219         # expand ld/st binary length/addr[:3] into unary bitmap
 220         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 221
 222         lds = Signal(reset_less=True)
 223         sts = Signal(reset_less=True)
 224         pi = self.pi
 225         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 226         comb += sts.eq(pi.is_st_i)  # st-req signals
 227
 228         # TODO: construct an MSRspec here and pass it over in
 229         # self.set_rd_addr and set_wr_addr below rather than just pr
 230         pr = ~pi.priv_mode
 231         dr = pi.virt_mode
 232         sf = ~pi.mode_32bit
 233         msr = MSRSpec(pr=pr, dr=dr, sf=sf)
 234
 235         # detect busy "edge"
 236         busy_delay = Signal()
 237         busy_edge = Signal()
 238         sync += busy_delay.eq(pi.busy_o)
 239         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 240
 241         # misalignment detection: bits at end of lenexpand are set.
 242         # when using the L0CacheBuffer "data expander" which splits requests
 243         # into *two* PortInterfaces, this acts as a "safety check".
 244         misalign = Signal()
 245         comb += misalign.eq(lenexp.lexp_o[8:].bool())
 246
 247
 248         # activate mode: only on "edge"
 249         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 250         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 251
 252         # LD/ST requested activates "busy" (only if not already busy)
 253         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 254             comb += busy_l.s.eq(~busy_delay)
 255             with m.If(self.pi.exc_o.happened):
 256                 sync += Display("fast exception")
 257
 258         # if now in "LD" mode: wait for addr_ok, then send the address out
 259         # to memory, acknowledge address, and send out LD data
 260         with m.If(ld_active.q):
 261             # set up LenExpander with the LD len and lower bits of addr
 262             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 263             comb += lenexp.len_i.eq(pi.data_len)
 264             comb += lenexp.addr_i.eq(lsbaddr)
 265             with m.If(pi.addr.ok & adrok_l.qn):
 266                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, msr)
 267                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 268                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 269
 270         # if now in "ST" mode: likewise do the same but with "ST"
 271         # to memory, acknowledge address, and send out LD data
 272         with m.If(st_active.q):
 273             # set up LenExpander with the ST len and lower bits of addr
 274             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 275             comb += lenexp.len_i.eq(pi.data_len)
 276             comb += lenexp.addr_i.eq(lsbaddr)
 277             with m.If(pi.addr.ok):
 278                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, msr,
 279                                  pi.is_dcbz_i)
 280                 with m.If(adrok_l.qn & self.pi.exc_o.happened==0):
 281                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 282                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 283
 284         # for LD mode, when addr has been "ok'd", assume that (because this
 285         # is a "Memory" test-class) the memory read data is valid.
 286         comb += reset_l.s.eq(0)
 287         comb += reset_l.r.eq(0)
 288         lddata = Signal(self.regwid, reset_less=True)
 289         data, ldok = self.get_rd_data(m)
 290         comb += lddata.eq((data & lenexp.rexp_o) >>
 291                           (lenexp.addr_i*8))
 292         with m.If(ld_active.q & adrok_l.q):
 293             # shift data down before pushing out.  requires masking
 294             # from the *byte*-expanded version of LenExpand output
 295             comb += pi.ld.data.eq(lddata)  # put data out
 296             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 297             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 298
 299         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 300         sync += st_done.s.eq(0)     # store done trigger
 301         with m.If(st_active.q & pi.st.ok):
 302             # shift data up before storing.  lenexp *bit* version of mask is
 303             # passed straight through as byte-level "write-enable" lines.
 304             stdata = Signal(self.regwid, reset_less=True)
 305             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 306             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 307             # and also handle the ready/stall/busy protocol
 308             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 309             sync += st_done.s.eq(~self.pi.exc_o.happened) # store done trigger
 310         with m.If(st_done.q):
 311             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 312
 313         # ugly hack, due to simultaneous addr req-go acknowledge
 314         reset_delay = Signal(reset_less=True)
 315         sync += reset_delay.eq(reset_l.q)
 316         with m.If(reset_delay):
 317             comb += adrok_l.r.eq(1)     # address reset
 318
 319         # after waiting one cycle (reset_l is "sync" mode), reset the port
 320         with m.If(reset_l.q):
 321             comb += ld_active.r.eq(1)   # leave the LD active for 1 cycle
 322             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 323             comb += reset_l.r.eq(1)     # clear reset
 324             comb += adrok_l.r.eq(1)     # address reset
 325             comb += st_done.r.eq(1)     # store done reset
 326
 327         # monitor for an exception, clear busy immediately
 328         with m.If(self.pi.exc_o.happened):
 329             comb += busy_l.r.eq(1)
 330             comb += reset_l.s.eq(1) # also reset whole unit
 331
 332         # however ST needs one cycle before busy is reset
 333         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 334         with m.If(reset_l.s):
 335             comb += cyc_l.s.eq(1)
 336
 337         with m.If(cyc_l.q):
 338             comb += cyc_l.r.eq(1)
 339             comb += busy_l.r.eq(1)
 340
 341         # busy latch outputs to interface
 342         if hasattr(self, "external_busy"):
 343             # when there is an extra (external) busy, include that here.
 344             # this is used e.g. in LoadStore1 when an instruction fault
 345             # is being processed (instr_fault) and stops Load/Store requests
 346             # from being made until it's done
 347             comb += pi.busy_o.eq(busy_l.q | self.external_busy(m))
 348         else:
 349             comb += pi.busy_o.eq(busy_l.q)
 350
 351         return m
 352
 353     def ports(self):
 354         yield from self.pi.ports()
 355
 356
 357 class TestMemoryPortInterface(PortInterfaceBase):
 358     """TestMemoryPortInterface
 359
 360     This is a test class for simple verification of the LDSTCompUnit
 361     and for the simple core, to be able to run unit tests rapidly and
 362     with less other code in the way.
 363
 364     Versions of this which are *compatible* (conform with PortInterface)
 365     will include augmented-Wishbone Bus versions, including ones that
 366     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 367     possible version that complies with PortInterface".
 368     """
 369
 370     def __init__(self, regwid=64, addrwid=4):
 371         super().__init__(regwid, addrwid)
 372         # hard-code memory addressing width to 6 bits
 373         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 374
 375     def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz):
 376         lsbaddr, msbaddr = self.splitaddr(addr)
 377         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 378
 379     def set_rd_addr(self, m, addr, mask, misalign, msr):
 380         lsbaddr, msbaddr = self.splitaddr(addr)
 381         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 382
 383     def set_wr_data(self, m, data, wen):
 384         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 385         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 386         return Const(1, 1)
 387
 388     def get_rd_data(self, m):
 389         return self.mem.rdport.data, Const(1, 1)
 390
 391     def elaborate(self, platform):
 392         m = super().elaborate(platform)
 393
 394         # add TestMemory as submodule
 395         m.submodules.mem = self.mem
 396
 397         return m
 398
 399     def ports(self):
 400         yield from super().ports()
 401         # TODO: memory ports