src/soc/fu/logical/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14 from soc.fu.logical.pipeline import LogicalBasePipe
  15 from soc.fu.logical.pipe_data import LogicalPipeSpec
  16 import random
  17
  18
  19 class TestCase:
  20     def __init__(self, program, regs, sprs, name):
  21         self.program = program
  22         self.regs = regs
  23         self.sprs = sprs
  24         self.name = name
  25
  26 def get_cu_inputs(dec2, sim):
  27     """naming (res) must conform to LogicalFunctionUnit input regspec
  28     """
  29     res = {}
  30
  31     # RA (or RC)
  32     reg1_ok = yield dec2.e.read_reg1.ok
  33     if reg1_ok:
  34         data1 = yield dec2.e.read_reg1.data
  35         res['ra'] = sim.gpr(data1).value
  36
  37     # RB (or immediate)
  38     reg2_ok = yield dec2.e.read_reg2.ok
  39     #imm_ok = yield dec2.e.imm_data.imm_ok
  40     if reg2_ok:
  41         data2 = yield dec2.e.read_reg2.data
  42         data2 = sim.gpr(data2).value
  43         res['rb'] = data2
  44     #elif imm_ok:
  45     #    data2 = yield dec2.e.imm_data.imm
  46     #    res['rb'] = data2
  47
  48     return res
  49
  50
  51 def set_alu_inputs(alu, dec2, sim):
  52     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  53     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  54     # and place it into data_i.b
  55
  56     inp = yield from get_cu_inputs(dec2, sim)
  57     if 'ra' in inp:
  58         yield alu.p.data_i.a.eq(inp['ra'])
  59     if 'rb' in inp:
  60         yield alu.p.data_i.b.eq(inp['rb'])
  61     imm_ok = yield dec2.e.imm_data.imm_ok
  62     if imm_ok:
  63         data2 = yield dec2.e.imm_data.imm
  64         yield alu.p.data_i.b.eq(data2)
  65
  66
  67 # This test bench is a bit different than is usual. Initially when I
  68 # was writing it, I had all of the tests call a function to create a
  69 # device under test and simulator, initialize the dut, run the
  70 # simulation for ~2 cycles, and assert that the dut output what it
  71 # should have. However, this was really slow, since it needed to
  72 # create and tear down the dut and simulator for every test case.
  73
  74 # Now, instead of doing that, every test case in ALUTestCase puts some
  75 # data into the test_data list below, describing the instructions to
  76 # be tested and the initial state. Once all the tests have been run,
  77 # test_data gets passed to TestRunner which then sets up the DUT and
  78 # simulator once, runs all the data through it, and asserts that the
  79 # results match the pseudocode sim at every cycle.
  80
  81 # By doing this, I've reduced the time it takes to run the test suite
  82 # massively. Before, it took around 1 minute on my computer, now it
  83 # takes around 3 seconds
  84
  85 test_data = []
  86
  87
  88 class LogicalTestCase(FHDLTestCase):
  89     def __init__(self, name):
  90         super().__init__(name)
  91         self.test_name = name
  92
  93     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
  94         tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
  95         test_data.append(tc)
  96
  97     def test_rand(self):
  98         insns = ["and", "or", "xor"]
  99         for i in range(40):
 100             choice = random.choice(insns)
 101             lst = [f"{choice} 3, 1, 2"]
 102             initial_regs = [0] * 32
 103             initial_regs[1] = random.randint(0, (1 << 64)-1)
 104             initial_regs[2] = random.randint(0, (1 << 64)-1)
 105             self.run_tst_program(Program(lst), initial_regs)
 106
 107     def test_rand_imm_logical(self):
 108         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
 109         for i in range(10):
 110             choice = random.choice(insns)
 111             imm = random.randint(0, (1 << 16)-1)
 112             lst = [f"{choice} 3, 1, {imm}"]
 113             print(lst)
 114             initial_regs = [0] * 32
 115             initial_regs[1] = random.randint(0, (1 << 64)-1)
 116             self.run_tst_program(Program(lst), initial_regs)
 117
 118     def test_cntz(self):
 119         insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
 120         for i in range(100):
 121             choice = random.choice(insns)
 122             lst = [f"{choice} 3, 1"]
 123             print(lst)
 124             initial_regs = [0] * 32
 125             initial_regs[1] = random.randint(0, (1 << 64)-1)
 126             self.run_tst_program(Program(lst), initial_regs)
 127
 128     def test_parity(self):
 129         insns = ["prtyw", "prtyd"]
 130         for i in range(10):
 131             choice = random.choice(insns)
 132             lst = [f"{choice} 3, 1"]
 133             print(lst)
 134             initial_regs = [0] * 32
 135             initial_regs[1] = random.randint(0, (1 << 64)-1)
 136             self.run_tst_program(Program(lst), initial_regs)
 137
 138     def test_popcnt(self):
 139         insns = ["popcntb", "popcntw", "popcntd"]
 140         for i in range(10):
 141             choice = random.choice(insns)
 142             lst = [f"{choice} 3, 1"]
 143             print(lst)
 144             initial_regs = [0] * 32
 145             initial_regs[1] = random.randint(0, (1 << 64)-1)
 146             self.run_tst_program(Program(lst), initial_regs)
 147
 148     def test_popcnt_edge(self):
 149         insns = ["popcntb", "popcntw", "popcntd"]
 150         for choice in insns:
 151             lst = [f"{choice} 3, 1"]
 152             initial_regs = [0] * 32
 153             initial_regs[1] = -1
 154             self.run_tst_program(Program(lst), initial_regs)
 155
 156     def test_cmpb(self):
 157         lst = ["cmpb 3, 1, 2"]
 158         initial_regs = [0] * 32
 159         initial_regs[1] = 0xdeadbeefcafec0de
 160         initial_regs[2] = 0xd0adb0000afec1de
 161         self.run_tst_program(Program(lst), initial_regs)
 162
 163     def test_bpermd(self):
 164         lst = ["bpermd 3, 1, 2"]
 165         for i in range(20):
 166             initial_regs = [0] * 32
 167             initial_regs[1] = 1<<random.randint(0,63)
 168             initial_regs[2] = 0xdeadbeefcafec0de
 169             self.run_tst_program(Program(lst), initial_regs)
 170
 171     def test_ilang(self):
 172         pspec = LogicalPipeSpec(id_wid=2)
 173         alu = LogicalBasePipe(pspec)
 174         vl = rtlil.convert(alu, ports=alu.ports())
 175         with open("logical_pipeline.il", "w") as f:
 176             f.write(vl)
 177
 178
 179 class TestRunner(FHDLTestCase):
 180     def __init__(self, test_data):
 181         super().__init__("run_all")
 182         self.test_data = test_data
 183
 184     def run_all(self):
 185         m = Module()
 186         comb = m.d.comb
 187         instruction = Signal(32)
 188
 189         pdecode = create_pdecode()
 190
 191         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 192
 193         pspec = LogicalPipeSpec(id_wid=2)
 194         m.submodules.alu = alu = LogicalBasePipe(pspec)
 195
 196         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 197         comb += alu.p.valid_i.eq(1)
 198         comb += alu.n.ready_i.eq(1)
 199         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 200         sim = Simulator(m)
 201
 202         sim.add_clock(1e-6)
 203
 204         def process():
 205             for test in self.test_data:
 206                 print(test.name)
 207                 program = test.program
 208                 self.subTest(test.name)
 209                 simulator = ISA(pdecode2, test.regs, test.sprs, 0)
 210                 gen = program.generate_instructions()
 211                 instructions = list(zip(gen, program.assembly.splitlines()))
 212
 213                 index = simulator.pc.CIA.value//4
 214                 while index < len(instructions):
 215                     ins, code = instructions[index]
 216
 217                     print("0x{:X}".format(ins & 0xffffffff))
 218                     print(code)
 219
 220                     # ask the decoder to decode this binary data (endian'd)
 221                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 222                     yield instruction.eq(ins)          # raw binary instr.
 223                     yield Settle()
 224                     fn_unit = yield pdecode2.e.fn_unit
 225                     self.assertEqual(fn_unit, Function.LOGICAL.value, code)
 226                     yield from set_alu_inputs(alu, pdecode2, simulator)
 227                     yield
 228                     opname = code.split(' ')[0]
 229                     yield from simulator.call(opname)
 230                     index = simulator.pc.CIA.value//4
 231
 232                     vld = yield alu.n.valid_o
 233                     while not vld:
 234                         yield
 235                         vld = yield alu.n.valid_o
 236                     yield
 237                     alu_out = yield alu.n.data_o.o.data
 238                     out_reg_valid = yield pdecode2.e.write_reg.ok
 239                     if out_reg_valid:
 240                         write_reg_idx = yield pdecode2.e.write_reg.data
 241                         expected = simulator.gpr(write_reg_idx).value
 242                         print(f"expected {expected:x}, actual: {alu_out:x}")
 243                         self.assertEqual(expected, alu_out, code)
 244                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 245                                                             simulator, code)
 246
 247         sim.add_sync_process(process)
 248         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 249                            traces=[]):
 250             sim.run()
 251
 252     def check_extra_alu_outputs(self, alu, dec2, sim, code):
 253         rc = yield dec2.e.rc.data
 254         if rc:
 255             cr_expected = sim.crl[0].get_range().value
 256             cr_actual = yield alu.n.data_o.cr0.data
 257             self.assertEqual(cr_expected, cr_actual, code)
 258
 259
 260 if __name__ == "__main__":
 261     unittest.main(exit=False)
 262     suite = unittest.TestSuite()
 263     suite.addTest(TestRunner(test_data))
 264
 265     runner = unittest.TextTestRunner()
 266     runner.run(suite)