src/soc/fu/shift_rot/test/test_pipe_caller.py

   1 import random
   2 from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
   3 from soc.fu.alu.alu_input_record import CompALUOpSubset
   4 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
   5 from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers
   6 from soc.config.endian import bigendian
   7 from openpower.decoder.isa.all import ISA
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.selectable_int import SelectableInt
  10 from openpower.decoder.power_enums import (XER_bits, Function, CryIn)
  11 from openpower.decoder.power_decoder2 import (PowerDecode2)
  12 from openpower.decoder.power_decoder import (create_pdecode)
  13 from openpower.decoder.isa.caller import ISACaller, special_sprs
  14 import unittest
  15 from nmigen.cli import rtlil
  16 from nmigen import Module, Signal
  17
  18 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  19 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  20 from nmutil.sim_tmp_alternative import Simulator, Settle
  21
  22
  23 def get_cu_inputs(dec2, sim):
  24     """naming (res) must conform to ShiftRotFunctionUnit input regspec
  25     """
  26     res = {}
  27
  28     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
  29     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
  30     yield from ALUHelpers.get_sim_int_rc(res, sim, dec2)  # RC
  31     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2)  # XER.ca
  32     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
  33
  34     print("alu get_cu_inputs", res)
  35
  36     return res
  37
  38
  39 def set_alu_inputs(alu, dec2, sim):
  40     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  41     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  42     # and place it into data_i.b
  43
  44     inp = yield from get_cu_inputs(dec2, sim)
  45     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  46     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  47     yield from ALUHelpers.set_int_rc(alu, dec2, inp)
  48     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  49     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  50
  51
  52 # This test bench is a bit different than is usual. Initially when I
  53 # was writing it, I had all of the tests call a function to create a
  54 # device under test and simulator, initialize the dut, run the
  55 # simulation for ~2 cycles, and assert that the dut output what it
  56 # should have. However, this was really slow, since it needed to
  57 # create and tear down the dut and simulator for every test case.
  58
  59 # Now, instead of doing that, every test case in ShiftRotTestCase puts some
  60 # data into the test_data list below, describing the instructions to
  61 # be tested and the initial state. Once all the tests have been run,
  62 # test_data gets passed to TestRunner which then sets up the DUT and
  63 # simulator once, runs all the data through it, and asserts that the
  64 # results match the pseudocode sim at every cycle.
  65
  66 # By doing this, I've reduced the time it takes to run the test suite
  67 # massively. Before, it took around 1 minute on my computer, now it
  68 # takes around 3 seconds
  69
  70
  71 class ShiftRotTestCase(TestAccumulatorBase):
  72
  73     def case_0_proof_regression_rlwnm(self):
  74         lst = ["rlwnm 3, 1, 2, 16, 20"]
  75         initial_regs = [0] * 32
  76         initial_regs[1] = 0x7ffdbffb91b906b9
  77         initial_regs[2] = 31
  78         print(initial_regs[1], initial_regs[2])
  79         self.add_case(Program(lst, bigendian), initial_regs)
  80
  81     def case_regression_rldicr_0(self):
  82         lst = ["rldicr. 29, 19, 1, 21"]
  83         initial_regs = [0] * 32
  84         initial_regs[1] = 0x3f
  85         initial_regs[19] = 0x00000000ffff8000
  86
  87         initial_sprs = {'XER': 0xe00c0000}
  88
  89         self.add_case(Program(lst, bigendian), initial_regs,
  90                                 initial_sprs=initial_sprs)
  91
  92     def case_regression_rldicr_1(self):
  93         lst = ["rldicr. 29, 19, 1, 21"]
  94         initial_regs = [0] * 32
  95         initial_regs[1] = 0x3f
  96         initial_regs[19] = 0x00000000ffff8000
  97
  98         self.add_case(Program(lst, bigendian), initial_regs)
  99
 100     def case_shift(self):
 101         insns = ["slw", "sld", "srw", "srd", "sraw", "srad"]
 102         for i in range(20):
 103             choice = random.choice(insns)
 104             lst = [f"{choice} 3, 1, 2"]
 105             initial_regs = [0] * 32
 106             initial_regs[1] = random.randint(0, (1 << 64)-1)
 107             initial_regs[2] = random.randint(0, 63)
 108             print(initial_regs[1], initial_regs[2])
 109             self.add_case(Program(lst, bigendian), initial_regs)
 110
 111     def case_shift_arith(self):
 112         lst = ["sraw 3, 1, 2"]
 113         initial_regs = [0] * 32
 114         initial_regs[1] = random.randint(0, (1 << 64)-1)
 115         initial_regs[2] = random.randint(0, 63)
 116         print(initial_regs[1], initial_regs[2])
 117         self.add_case(Program(lst, bigendian), initial_regs)
 118
 119     def case_sld_rb_too_big(self):
 120         lst = ["sld 3, 1, 4",
 121                ]
 122         initial_regs = [0] * 32
 123         initial_regs[1] = 0xffffffffffffffff
 124         initial_regs[4] = 64 # too big, output should be zero
 125         self.add_case(Program(lst, bigendian), initial_regs)
 126
 127     def case_sld_rb_is_zero(self):
 128         lst = ["sld 3, 1, 4",
 129                ]
 130         initial_regs = [0] * 32
 131         initial_regs[1] = 0x8000000000000000
 132         initial_regs[4] = 0 # no shift; output should equal input
 133         self.add_case(Program(lst, bigendian), initial_regs)
 134
 135     def case_shift_once(self):
 136         lst = ["slw 3, 1, 4",
 137                "slw 3, 1, 2"]
 138         initial_regs = [0] * 32
 139         initial_regs[1] = 0x80000000
 140         initial_regs[2] = 0x40
 141         initial_regs[4] = 0x00
 142         self.add_case(Program(lst, bigendian), initial_regs)
 143
 144     def case_rlwinm(self):
 145         for i in range(10):
 146             mb = random.randint(0, 31)
 147             me = random.randint(0, 31)
 148             sh = random.randint(0, 31)
 149             lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}",
 150                    #f"rlwinm. 3, 1, {mb}, {me}, {sh}"
 151                    ]
 152             initial_regs = [0] * 32
 153             initial_regs[1] = random.randint(0, (1 << 64)-1)
 154             self.add_case(Program(lst, bigendian), initial_regs)
 155
 156     def case_rlwimi(self):
 157         lst = ["rlwimi 3, 1, 5, 20, 6"]
 158         initial_regs = [0] * 32
 159         initial_regs[1] = 0xdeadbeef
 160         initial_regs[3] = 0x12345678
 161         self.add_case(Program(lst, bigendian), initial_regs)
 162
 163     def case_rlwnm(self):
 164         lst = ["rlwnm 3, 1, 2, 20, 6"]
 165         initial_regs = [0] * 32
 166         initial_regs[1] = random.randint(0, (1 << 64)-1)
 167         initial_regs[2] = random.randint(0, 63)
 168         self.add_case(Program(lst, bigendian), initial_regs)
 169
 170     def case_rldicl(self):
 171         lst = ["rldicl 3, 1, 5, 20"]
 172         initial_regs = [0] * 32
 173         initial_regs[1] = random.randint(0, (1 << 64)-1)
 174         self.add_case(Program(lst, bigendian), initial_regs)
 175
 176     def case_rldicr(self):
 177         lst = ["rldicr 3, 1, 5, 20"]
 178         initial_regs = [0] * 32
 179         initial_regs[1] = random.randint(0, (1 << 64)-1)
 180         self.add_case(Program(lst, bigendian), initial_regs)
 181
 182     def case_regression_extswsli(self):
 183         lst = [f"extswsli 3, 1, 34"]
 184         initial_regs = [0] * 32
 185         initial_regs[1] = 0x5678
 186         self.add_case(Program(lst, bigendian), initial_regs)
 187
 188     def case_regression_extswsli_2(self):
 189         lst = [f"extswsli 3, 1, 7"]
 190         initial_regs = [0] * 32
 191         initial_regs[1] = 0x3ffffd7377f19fdd
 192         self.add_case(Program(lst, bigendian), initial_regs)
 193
 194     def case_regression_extswsli_3(self):
 195         lst = [f"extswsli 3, 1, 0"]
 196         initial_regs = [0] * 32
 197         #initial_regs[1] = 0x80000000fb4013e2
 198         #initial_regs[1] = 0xffffffffffffffff
 199         #initial_regs[1] = 0x00000000ffffffff
 200         initial_regs[1] = 0x0000010180122900
 201         #initial_regs[1] = 0x3ffffd73f7f19fdd
 202         self.add_case(Program(lst, bigendian), initial_regs)
 203
 204     def case_extswsli(self):
 205         for i in range(40):
 206             sh = random.randint(0, 63)
 207             lst = [f"extswsli 3, 1, {sh}"]
 208             initial_regs = [0] * 32
 209             initial_regs[1] = random.randint(0, (1 << 64)-1)
 210             self.add_case(Program(lst, bigendian), initial_regs)
 211
 212     def case_rlc(self):
 213         insns = ["rldic", "rldicl", "rldicr"]
 214         for i in range(20):
 215             choice = random.choice(insns)
 216             sh = random.randint(0, 63)
 217             m = random.randint(0, 63)
 218             lst = [f"{choice} 3, 1, {sh}, {m}"]
 219             initial_regs = [0] * 32
 220             initial_regs[1] = random.randint(0, (1 << 64)-1)
 221             self.add_case(Program(lst, bigendian), initial_regs)
 222
 223     def case_ilang(self):
 224         pspec = ShiftRotPipeSpec(id_wid=2)
 225         alu = ShiftRotBasePipe(pspec)
 226         vl = rtlil.convert(alu, ports=alu.ports())
 227         with open("shift_rot_pipeline.il", "w") as f:
 228             f.write(vl)
 229
 230
 231 class TestRunner(unittest.TestCase):
 232     def __init__(self, test_data):
 233         super().__init__("run_all")
 234         self.test_data = test_data
 235
 236     def execute(self, alu, instruction, pdecode2, test):
 237         program = test.program
 238         simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
 239                         test.mem, test.msr,
 240                         bigendian=bigendian)
 241         gen = program.generate_instructions()
 242         instructions = list(zip(gen, program.assembly.splitlines()))
 243
 244         index = simulator.pc.CIA.value//4
 245         while index < len(instructions):
 246             ins, code = instructions[index]
 247
 248             print("0x{:X}".format(ins & 0xffffffff))
 249             print(code)
 250
 251             # ask the decoder to decode this binary data (endian'd)
 252             yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
 253             yield instruction.eq(ins)          # raw binary instr.
 254             yield Settle()
 255             fn_unit = yield pdecode2.e.do.fn_unit
 256             self.assertEqual(fn_unit, Function.SHIFT_ROT.value)
 257             yield from set_alu_inputs(alu, pdecode2, simulator)
 258
 259             # set valid for one cycle, propagate through pipeline...
 260             yield alu.p.valid_i.eq(1)
 261             yield
 262             yield alu.p.valid_i.eq(0)
 263
 264             opname = code.split(' ')[0]
 265             yield from simulator.call(opname)
 266             index = simulator.pc.CIA.value//4
 267
 268             vld = yield alu.n.valid_o
 269             while not vld:
 270                 yield
 271                 vld = yield alu.n.valid_o
 272             yield
 273             alu_out = yield alu.n.data_o.o.data
 274
 275             yield from self.check_alu_outputs(alu, pdecode2,
 276                                               simulator, code)
 277             yield Settle()
 278
 279     def run_all(self):
 280         m = Module()
 281         comb = m.d.comb
 282         instruction = Signal(32)
 283
 284         fn_name = "SHIFT_ROT"
 285         opkls = ShiftRotPipeSpec.opsubsetkls
 286
 287         m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
 288         pdecode = pdecode2.dec
 289
 290         pspec = ShiftRotPipeSpec(id_wid=2)
 291         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
 292
 293         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
 294         comb += alu.n.ready_i.eq(1)
 295         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 296         sim = Simulator(m)
 297
 298         sim.add_clock(1e-6)
 299
 300         def process():
 301             for test in self.test_data:
 302                 print(test.name)
 303                 program = test.program
 304                 with self.subTest(test.name):
 305                     yield from self.execute(alu, instruction, pdecode2, test)
 306
 307         sim.add_sync_process(process)
 308         with sim.write_vcd("shift_rot_simulator.vcd"):
 309             sim.run()
 310
 311     def check_alu_outputs(self, alu, dec2, sim, code):
 312
 313         rc = yield dec2.e.do.rc.rc
 314         cridx_ok = yield dec2.e.write_cr.ok
 315         cridx = yield dec2.e.write_cr.data
 316
 317         print("check extra output", repr(code), cridx_ok, cridx)
 318         if rc:
 319             self.assertEqual(cridx, 0, code)
 320
 321         sim_o = {}
 322         res = {}
 323
 324         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 325         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
 326         yield from ALUHelpers.get_int_o(res, alu, dec2)
 327
 328         print ("hw outputs", res)
 329
 330         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 331         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 332         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 333
 334         print ("sim outputs", sim_o)
 335
 336         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 337         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 338         ALUHelpers.check_int_o(self, res, sim_o, code)
 339
 340
 341 if __name__ == "__main__":
 342     unittest.main(exit=False)
 343     suite = unittest.TestSuite()
 344     suite.addTest(TestRunner(ShiftRotTestCase().test_data))
 345
 346     runner = unittest.TextTestRunner()
 347     runner.run(suite)