3 from migen
import ClockSignal
, ResetSignal
, Signal
, Instance
, Cat
5 from litex
.soc
.interconnect
import wishbone
as wb
6 from litex
.soc
.cores
.cpu
import CPU
8 from soc
.config
.pinouts
import get_pinspecs
9 from soc
.debug
.jtag
import Pins
10 from c4m
.nmigen
.jtag
.tap
import IOType
12 from libresoc
.ls180
import io
13 from litex
.build
.generic_platform
import ConstraintManager
16 CPU_VARIANTS
= ["standard", "standard32", "standardjtag",
17 "standardjtagtestgpio", "ls180",
21 def make_wb_bus(prefix
, obj
, simple
=False):
23 outpins
= ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
25 outpins
+= ['cti', 'bte']
27 res
['o_%s__%s' % (prefix
, o
)] = getattr(obj
, o
)
28 for i
in ['ack', 'err', 'dat_r']:
29 res
['i_%s__%s' % (prefix
, i
)] = getattr(obj
, i
)
32 def make_wb_slave(prefix
, obj
):
34 for i
in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
35 res
['i_%s__%s' % (prefix
, i
)] = getattr(obj
, i
)
36 for o
in ['ack', 'err', 'dat_r']:
37 res
['o_%s__%s' % (prefix
, o
)] = getattr(obj
, o
)
40 def make_pad(res
, dirn
, name
, suffix
, cpup
, iop
):
41 print ("make pad", dirn
, name
, suffix
, cpup
, iop
)
42 cpud
, iod
= ('i', 'o') if dirn
else ('o', 'i')
43 res
['%s_%s__core__%s' % (cpud
, name
, suffix
)] = cpup
44 res
['%s_%s__pad__%s' % (iod
, name
, suffix
)] = iop
46 def get_field(rec
, name
):
50 return getattr(rec
, f
)
53 def make_jtag_ioconn(res
, pin
, cpupads
, iopads
):
54 (fn
, pin
, iotype
, pin_name
, scan_idx
) = pin
55 #serial_tx__core__o, serial_rx__pad__i,
56 # special-case sdram_clock
57 if pin
== 'clock' and fn
== 'sdr':
58 cpu
= cpupads
['sdram_clock']
59 io
= iopads
['sdram_clock']
63 print ("cpupads", cpupads
)
64 print ("iopads", iopads
)
65 print ("pin", fn
, pin
, iotype
, pin_name
)
68 name
= "%s_%s" % (fn
, pin
)
72 if iotype
in (IOType
.In
, IOType
.Out
):
74 if pin
== 'clock' and fn
== 'sdr':
77 elif len(ps
) == 2 and ps
[-1].isdigit():
80 cpup
= getattr(cpu
, pin
)[idx
]
81 iop
= getattr(io
, pin
)[idx
]
87 cpup
= getattr(cpu
, pin
)
88 iop
= getattr(io
, pin
)
90 if iotype
== IOType
.Out
:
91 # output from the pad is routed through C4M JTAG and so
92 # is an *INPUT* into core. ls180soc connects this to "real" peripheral
93 make_pad(res
, True, name
, "o", cpup
, iop
)
95 elif iotype
== IOType
.In
:
96 # input to the pad is routed through C4M JTAG and so
97 # is an *OUTPUT* into core. ls180soc connects this to "real" peripheral
98 make_pad(res
, False, name
, "i", cpup
, iop
)
100 elif iotype
== IOType
.InTriOut
:
101 if fn
== 'gpio': # sigh decode GPIO special-case
104 elif fn
== 'sdr': # sigh
105 idx
= int(pin
.split('_')[-1])
110 print ("gpio tri", fn
, pin
, iotype
, pin_name
, scan_idx
, idx
)
111 cpup
, iop
= get_field(cpu
, "i")[idx
], get_field(io
, "i")[idx
]
112 make_pad(res
, False, name
, "i", cpup
, iop
)
113 cpup
, iop
= get_field(cpu
, "o")[idx
], get_field(io
, "o")[idx
]
114 make_pad(res
, True, name
, "o", cpup
, iop
)
115 cpup
, iop
= get_field(cpu
, "oe")[oe_idx
], get_field(io
, "oe")[oe_idx
]
116 make_pad(res
, True, name
, "oe", cpup
, iop
)
118 if iotype
in (IOType
.In
, IOType
.InTriOut
):
119 sigs
.append(("i", 1))
120 if iotype
in (IOType
.Out
, IOType
.TriOut
, IOType
.InTriOut
):
121 sigs
.append(("o", 1))
122 if iotype
in (IOType
.TriOut
, IOType
.InTriOut
):
123 sigs
.append(("oe", 1))
128 human_name
= "Libre-SoC"
129 variants
= CPU_VARIANTS
130 endianness
= "little"
131 gcc_triple
= ("powerpc64le-linux", "powerpc64le-linux-gnu")
132 linker_output_format
= "elf64-powerpcle"
134 io_regions
= {0xc0000000: 0x10000000} # origin, length
138 return {"csr": 0xc0000000}
143 flags
+= "-mabi=elfv2 "
144 flags
+= "-msoft-float "
145 flags
+= "-mno-string "
146 flags
+= "-mno-multiple "
148 flags
+= "-mno-altivec "
149 flags
+= "-mlittle-endian "
150 flags
+= "-mstrict-align "
151 flags
+= "-fno-stack-protector "
152 flags
+= "-mcmodel=small "
153 flags
+= "-D__microwatt__ "
156 def __init__(self
, platform
, variant
="standard"):
157 self
.platform
= platform
158 self
.variant
= variant
159 self
.reset
= Signal()
161 irq_en
= "noirq" not in variant
164 self
.interrupt
= Signal(16)
166 if variant
== "standard32":
168 self
.dbus
= dbus
= wb
.Interface(data_width
=32, adr_width
=30)
170 self
.dbus
= dbus
= wb
.Interface(data_width
=64, adr_width
=29)
172 self
.ibus
= ibus
= wb
.Interface(data_width
=64, adr_width
=29)
174 self
.xics_icp
= icp
= wb
.Interface(data_width
=32, adr_width
=30)
175 self
.xics_ics
= ics
= wb
.Interface(data_width
=32, adr_width
=30)
177 jtag_en
= ('jtag' in variant
) or variant
== 'ls180'
179 if "testgpio" in variant
:
180 self
.simple_gpio
= gpio
= wb
.Interface(data_width
=32, adr_width
=30)
182 self
.jtag_wb
= jtag_wb
= wb
.Interface(data_width
=64, adr_width
=29)
184 self
.periph_buses
= [ibus
, dbus
]
185 self
.memory_buses
= []
188 self
.periph_buses
.append(jtag_wb
)
189 self
.jtag_tck
= Signal(1)
190 self
.jtag_tms
= Signal(1)
191 self
.jtag_tdi
= Signal(1)
192 self
.jtag_tdo
= Signal(1)
194 self
.dmi_addr
= Signal(4)
195 self
.dmi_din
= Signal(64)
196 self
.dmi_dout
= Signal(64)
197 self
.dmi_wr
= Signal(1)
198 self
.dmi_ack
= Signal(1)
199 self
.dmi_req
= Signal(1)
203 self
.cpu_params
= dict(
205 i_clk
= ClockSignal(),
206 i_rst
= ResetSignal() | self
.reset
,
208 # Monitoring / Debugging
211 i_core_bigendian_i
= 0, # Signal(),
212 o_busy_o
= Signal(), # not connected
213 o_memerr_o
= Signal(), # not connected
214 o_pc_o
= Signal(64), # not connected
219 self
.cpu_params
['i_int_level_i'] = self
.interrupt
222 self
.cpu_params
.update(dict(
224 o_TAP_bus__tdo
= self
.jtag_tdo
,
225 i_TAP_bus__tdi
= self
.jtag_tdi
,
226 i_TAP_bus__tms
= self
.jtag_tms
,
227 i_TAP_bus__tck
= self
.jtag_tck
,
230 self
.cpu_params
.update(dict(
232 i_dmi_addr_i
= self
.dmi_addr
,
233 i_dmi_din
= self
.dmi_din
,
234 o_dmi_dout
= self
.dmi_dout
,
235 i_dmi_req_i
= self
.dmi_req
,
236 i_dmi_we_i
= self
.dmi_wr
,
237 o_dmi_ack_o
= self
.dmi_ack
,
240 # add clock select, pll output
241 if variant
== "ls180":
242 self
.pll_18_o
= Signal()
243 self
.clk_sel
= Signal(3)
244 self
.pll_lck_o
= Signal()
245 self
.cpu_params
['i_clk_sel_i'] = self
.clk_sel
246 self
.cpu_params
['o_pll_18_o'] = self
.pll_18_o
247 self
.cpu_params
['o_pll_lck_o'] = self
.pll_lck_o
249 # add wishbone buses to cpu params
250 self
.cpu_params
.update(make_wb_bus("ibus", ibus
))
251 self
.cpu_params
.update(make_wb_bus("dbus", dbus
))
252 self
.cpu_params
.update(make_wb_slave("ics_wb", ics
))
253 self
.cpu_params
.update(make_wb_slave("icp_wb", icp
))
254 if "testgpio" in variant
:
255 self
.cpu_params
.update(make_wb_slave("gpio_wb", gpio
))
257 self
.cpu_params
.update(make_wb_bus("jtag_wb", jtag_wb
, simple
=True))
259 if variant
== 'ls180':
260 # urr yuk. have to expose iopads / pins from core to litex
261 # then back again. cut _some_ of that out by connecting
262 self
.padresources
= io()
263 self
.pad_cm
= ConstraintManager(self
.padresources
, [])
267 subset
= {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
269 for periph
in subset
:
272 if periph
[-1].isdigit():
273 periph
, num
= periph
[:-1], int(periph
[-1])
274 print ("periph request", periph
, num
)
277 periph
, num
= 'spimaster', None
279 periph
, num
= 'spisdcard', None
280 elif periph
== 'sdr':
282 elif periph
== 'mtwi':
285 periph
, num
= 'sdcard', None
286 litexmap
[origperiph
] = (periph
, num
)
287 self
.cpupads
[origperiph
] = platform
.request(periph
, num
)
288 iopads
[origperiph
] = self
.pad_cm
.request(periph
, num
)
289 if periph
== 'sdram':
290 # special-case sdram clock
291 ck
= platform
.request("sdram_clock")
292 self
.cpupads
['sdram_clock'] = ck
293 ck
= self
.pad_cm
.request("sdram_clock")
294 iopads
['sdram_clock'] = ck
296 pinset
= get_pinspecs(subset
=subset
)
299 make_jtag_ioconn(self
.cpu_params
, pin
, self
.cpupads
, iopads
)
301 # add verilog sources
302 self
.add_sources(platform
)
304 def set_reset_address(self
, reset_address
):
305 assert not hasattr(self
, "reset_address")
306 self
.reset_address
= reset_address
307 assert reset_address
== 0x00000000
310 def add_sources(platform
):
311 cdir
= os
.path
.dirname(__file__
)
312 platform
.add_source(os
.path
.join(cdir
, "libresoc.v"))
314 def do_finalize(self
):
315 self
.specials
+= Instance("test_issuer", **self
.cpu_params
)