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Merge pull request #117 from riscv/multicore_debug
[riscv-isa-sim.git]
/
config.h.in
diff --git
a/config.h.in
b/config.h.in
index 566b1bcc17ef985ec869081924df3db943cd1448..137f1950054e3e4b709a76233c2aadcee778c7cf 100644
(file)
--- a/
config.h.in
+++ b/
config.h.in
@@
-6,6
+6,9
@@
/* Default value for --isa switch */
#undef DEFAULT_ISA
/* Default value for --isa switch */
#undef DEFAULT_ISA
+/* Path to the device-tree-compiler */
+#undef DTC
+
/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
#undef DUMMY_ROCC_ENABLED
/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
#undef DUMMY_ROCC_ENABLED
@@
-72,6
+75,9
@@
/* Enable PC histogram generation */
#undef RISCV_ENABLE_HISTOGRAM
/* Enable PC histogram generation */
#undef RISCV_ENABLE_HISTOGRAM
+/* Enable hardware support for misaligned loads and stores */
+#undef RISCV_ENABLE_MISALIGNED
+
/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
#undef SOFTFLOAT_ENABLED
/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
#undef SOFTFLOAT_ENABLED