+ # XXX not obvious
+ b3 = Mux(load_store_address_low_2[1],
+ Mux(load_store_address_low_2[0], register_rs2[0:8],
+ register_rs2[8:16]),
+ Mux(load_store_address_low_2[0], register_rs2[16:24],
+ register_rs2[24:32]))
+ b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
+ register_rs2[16:24])
+ b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
+ register_rs2[8:16])
+ b0 = register_rs2[0:8]
+
+ self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
+
+ # XXX not obvious
+ unmasked_loaded_value = Signal(32)
+
+ b0 = Mux(load_store_address_low_2[1],
+ Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
+ mi.rw_data_out[16:24]),
+ Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
+ mi.rw_data_out[0:8]))
+ b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
+ mi.rw_data_out[8:16])
+ b23 = mi.rw_data_out[16:32]
+
+ self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
+
+ # XXX not obvious
+ loaded_value = Signal(32)
+
+ b0 = unmasked_loaded_value[0:8]
+ b1 = Mux(dc.funct3[0:2] == 0,
+ Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
+ unmasked_loaded_value[8:16])
+ b2 = Mux(dc.funct3[1] == 0,
+ Replicate(~dc.funct3[2] &
+ Mux(dc.funct3[0], unmasked_loaded_value[15],
+ unmasked_loaded_value[7]),
+ 16),
+ unmasked_loaded_value[16:32])
+
+ self.comb += loaded_value.eq(Cat(b0, b1, b2))
+
+ self.comb += mi.rw_active.eq(~self.reset
+ & (fetch_output_st == fetch_output_state_valid)
+ & ~load_store_misaligned
+ & ((dc.act & (DA.load | DA.store)) != 0))
+
+ self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
+
+ # alu
+ alu_a = Signal(32)
+ alu_b = Signal(32)
+ alu_result = Signal(32)
+
+ self.comb += alu_a.eq(register_rs1)
+ self.comb += alu_b.eq(Mux(dc.opcode[5],
+ register_rs2,
+ dc.immediate))
+