+ def __init__(self):
+ #self.clk = ClockSignal()
+ #self.reset = ResetSignal()
+ self.tty_write = Signal()
+ self.tty_write_data = Signal(8)
+ self.tty_write_busy = Signal()
+ self.switch_2 = Signal()
+ self.switch_3 = Signal()
+ self.led_1 = Signal()
+ self.led_3 = Signal()
+
+ ram_size = Constant(0x8000)
+ ram_start = Constant(0x10000, 32)
+ reset_vector = Signal(32)
+ mtvec = Signal(32)
+
+ reset_vector.eq(ram_start)
+ mtvec.eq(ram_start + 0x40)
+
+ l = []
+ for i in range(31):
+ l.append(Signal(32, name="register%d" % i))
+ registers = Array(l)
+
+ mi = MemoryInterface()
+
+ mii = Instance("cpu_memory_interface", name="memory_instance",
+ p_ram_size = ram_size,
+ p_ram_start = ram_start,
+ i_clk=ClockSignal(),
+ i_rst=ResetSignal(),
+ i_fetch_address = mi.fetch_address,
+ o_fetch_data = mi.fetch_data,
+ o_fetch_valid = mi.fetch_valid,
+ i_rw_address = mi.rw_address,
+ i_rw_byte_mask = mi.rw_byte_mask,
+ i_rw_read_not_write = mi.rw_read_not_write,
+ i_rw_active = mi.rw_active,
+ i_rw_data_in = mi.rw_data_in,
+ o_rw_data_out = mi.rw_data_out,
+ o_rw_address_valid = mi.rw_address_valid,
+ o_rw_wait = mi.rw_wait,
+ o_tty_write = self.tty_write,
+ o_tty_write_data = self.tty_write_data,
+ i_tty_write_busy = self.tty_write_busy,
+ i_switch_2 = self.switch_2,
+ i_switch_3 = self.switch_3,
+ o_led_1 = self.led_1,
+ o_led_3 = self.led_3
+ )
+ self.specials += mii
+
+ fetch_act = Signal(fetch_action)
+ fetch_target_pc = Signal(32)
+ fetch_output_pc = Signal(32)
+ fetch_output_instruction = Signal(32)
+ fetch_output_st = Signal(fetch_output_state)
+
+ fs = Instance("CPUFetchStage", name="fetch_stage",
+ i_clk=ClockSignal(),
+ i_rst=ResetSignal(),
+ o_memory_interface_fetch_address = mi.fetch_address,
+ i_memory_interface_fetch_data = mi.fetch_data,
+ i_memory_interface_fetch_valid = mi.fetch_valid,
+ i_fetch_action = fetch_act,
+ i_target_pc = fetch_target_pc,
+ o_output_pc = fetch_output_pc,
+ o_output_instruction = fetch_output_instruction,
+ o_output_state = fetch_output_st,
+ i_reset_vector = reset_vector,
+ i_mtvec = mtvec,
+ )
+ self.specials += fs
+
+ decoder_funct7 = Signal(7)
+ decoder_funct3 = Signal(3)
+ decoder_rd = Signal(5)
+ decoder_rs1 = Signal(5)
+ decoder_rs2 = Signal(5)
+ decoder_immediate = Signal(32)
+ decoder_opcode = Signal(7)
+ decode_act = Signal(decode_action)
+
+ cd = Instance("CPUDecoder", name="decoder",
+ i_instruction = fetch_output_instruction,
+ o_funct7 = decoder_funct7,
+ o_funct3 = decoder_funct3,
+ o_rd = decoder_rd,
+ o_rs1 = decoder_rs1,
+ o_rs2 = decoder_rs2,
+ o_immediate = decoder_immediate,
+ o_opcode = decoder_opcode,
+ o_decode_action = decode_act
+ )
+ self.specials += cd
+
+ register_rs1 = Signal(32)
+ register_rs2 = Signal(32)
+ self.comb += If(decoder_rs1 == 0,
+ register_rs1.eq(0)
+ ).Else(
+ register_rs1.eq(registers[decoder_rs1-1]))
+ self.comb += If(decoder_rs2 == 0,
+ register_rs2.eq(0)
+ ).Else(
+ register_rs2.eq(registers[decoder_rs2-1]))
+
+ load_store_address = Signal(32)
+ load_store_address_low_2 = Signal(2)
+
+ self.comb += load_store_address.eq(decoder_immediate + register_rs1)
+ self.comb += load_store_address_low_2.eq(
+ decoder_immediate[:2] + register_rs1[:2])
+
+ load_store_misaligned = Signal()
+
+ lsa = self.get_ls_misaligned(load_store_misaligned, decoder_funct3,
+ load_store_address_low_2)
+ self.comb += lsa
+
+ # XXX rwaddr not 31:2 any more
+ self.comb += mi.rw_address.eq(load_store_address[2:])
+
+ unshifted_load_store_byte_mask = Signal(4)
+
+ self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(
+ decoder_funct3))
+
+ # XXX yuck. this will cause migen simulation to fail
+ # (however conversion to verilog works)
+ self.comb += mi.rw_byte_mask.eq(
+ _Operator("<<", [unshifted_load_store_byte_mask,
+ load_store_address_low_2]))