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move get_fetch_action to separate verilog file
[rv32.git]
/
cpu_decoder.py
diff --git
a/cpu_decoder.py
b/cpu_decoder.py
index 995a04c1a4d9db41cb7d58912b142d38f9519d64..c92fb8898daea15443b74c506b45efc328ed603e 100644
(file)
--- a/
cpu_decoder.py
+++ b/
cpu_decoder.py
@@
-154,7
+154,7
@@
class CPUDecoder(Module):
return self._decode_funct3(DA.jalr, [F3.jalr, ])
def calculate_op_action(self):
return self._decode_funct3(DA.jalr, [F3.jalr, ])
def calculate_op_action(self):
- """ decode op action
+ """ decode op action
: the arith ops, and, or, add, xor, sr/sl etc.
"""
c = {}
immz = Constant(0, 12)
"""
c = {}
immz = Constant(0, 12)
@@
-178,7
+178,7
@@
class CPUDecoder(Module):
return Case(self.funct3, c)
def calculate_misc_action(self):
return Case(self.funct3, c)
def calculate_misc_action(self):
- """ decode misc mem action
+ """ decode misc mem action
: fence and fence_i
"""
c = {}
immz = Constant(0, 12)
"""
c = {}
immz = Constant(0, 12)
@@
-203,14
+203,14
@@
class CPUDecoder(Module):
return Case(self.funct3, c)
def calculate_system_action(self):
return Case(self.funct3, c)
def calculate_system_action(self):
- """ decode
system action
+ """ decode
opcode system: ebreak and csrs
"""
c = {}
b1 = Constant(1, 32)
regz = Constant(0, 5)
# ebreak
c[F3.ecall_ebreak] = \
"""
c = {}
b1 = Constant(1, 32)
regz = Constant(0, 5)
# ebreak
c[F3.ecall_ebreak] = \
- If((self.immediate == ~b1)
^
(self.rs1 == regz) & \
+ If((self.immediate == ~b1)
&
(self.rs1 == regz) & \
(self.rd == regz),
self.decode_action.eq(DA.trap_ecall_ebreak)
).Else(
(self.rd == regz),
self.decode_action.eq(DA.trap_ecall_ebreak)
).Else(