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Implement clearing-misa.C-while-PC-is-misaligned proposal
[riscv-isa-sim.git]
/
riscv
/
decode.h
diff --git
a/riscv/decode.h
b/riscv/decode.h
index 7f5effc741933b9a3b97fba5f54992ce2dac477f..596a2ad9bfea1bfe24b38ed1b733e5a8c91bb688 100644
(file)
--- a/
riscv/decode.h
+++ b/
riscv/decode.h
@@
-201,18
+201,18
@@
private:
#define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
#define set_pc(x) \
#define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
#define set_pc(x) \
- do { if (unlikely(((x) & 2)) && !p->supports_extension('C')) \
- throw trap_instruction_address_misaligned(x); \
+ do { p->check_pc_alignment(x); \
npc = sext_xlen(x); \
} while(0)
#define set_pc_and_serialize(x) \
do { reg_t __npc = (x); \
npc = sext_xlen(x); \
} while(0)
#define set_pc_and_serialize(x) \
do { reg_t __npc = (x); \
- set_pc(__npc); /* check alignment */ \
npc = PC_SERIALIZE_AFTER; \
STATE.pc = __npc; \
} while(0)
npc = PC_SERIALIZE_AFTER; \
STATE.pc = __npc; \
} while(0)
+#define serialize() set_pc_and_serialize(npc)
+
/* Sentinel PC values to serialize simulator pipeline */
#define PC_SERIALIZE_BEFORE 3
#define PC_SERIALIZE_AFTER 5
/* Sentinel PC values to serialize simulator pipeline */
#define PC_SERIALIZE_BEFORE 3
#define PC_SERIALIZE_AFTER 5