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Implement clearing-misa.C-while-PC-is-misaligned proposal
[riscv-isa-sim.git]
/
riscv
/
insns
/
csrrsi.h
diff --git
a/riscv/insns/csrrsi.h
b/riscv/insns/csrrsi.h
index 90a44368b3344e67d13e36d1c3e8247cb204ea03..b673725b54d1cbc8eb0a4e27e4af7d6563eb45b6 100644
(file)
--- a/
riscv/insns/csrrsi.h
+++ b/
riscv/insns/csrrsi.h
@@
-1,4
+1,8
@@
-int csr = validate_csr(insn.csr(), true);
+bool write = insn.rs1() != 0;
+int csr = validate_csr(insn.csr(), write);
reg_t old = p->get_csr(csr);
reg_t old = p->get_csr(csr);
-p->set_csr(csr, old | insn.rs1());
+if (write) {
+ p->set_csr(csr, old | insn.rs1());
+}
WRITE_RD(sext_xlen(old));
WRITE_RD(sext_xlen(old));
+serialize();