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Include math.h for NAN (#137)
[riscv-isa-sim.git]
/
riscv
/
interactive.cc
diff --git
a/riscv/interactive.cc
b/riscv/interactive.cc
index 623c425c7f7f85b63f5a6eeb29506ae2f58de6ef..dbcd22455d5fe6fdb75388946df176d7227ca6df 100644
(file)
--- a/
riscv/interactive.cc
+++ b/
riscv/interactive.cc
@@
-17,6
+17,7
@@
#include <string>
#include <vector>
#include <algorithm>
#include <string>
#include <vector>
#include <algorithm>
+#include <math.h>
DECLARE_TRAP(-1, interactive)
DECLARE_TRAP(-1, interactive)
@@
-24,7
+25,7
@@
processor_t *sim_t::get_core(const std::string& i)
{
char *ptr;
unsigned long p = strtoul(i.c_str(), &ptr, 10);
{
char *ptr;
unsigned long p = strtoul(i.c_str(), &ptr, 10);
- if (*ptr || p >=
num_cores
())
+ if (*ptr || p >=
procs.size
())
throw trap_interactive();
return get_core(p);
}
throw trap_interactive();
return get_core(p);
}
@@
-66,6
+67,7
@@
void sim_t::interactive()
funcs["r"] = funcs["run"];
funcs["rs"] = &sim_t::interactive_run_silent;
funcs["reg"] = &sim_t::interactive_reg;
funcs["r"] = funcs["run"];
funcs["rs"] = &sim_t::interactive_run_silent;
funcs["reg"] = &sim_t::interactive_reg;
+ funcs["freg"] = &sim_t::interactive_freg;
funcs["fregs"] = &sim_t::interactive_fregs;
funcs["fregd"] = &sim_t::interactive_fregd;
funcs["pc"] = &sim_t::interactive_pc;
funcs["fregs"] = &sim_t::interactive_fregs;
funcs["fregd"] = &sim_t::interactive_fregd;
funcs["pc"] = &sim_t::interactive_pc;
@@
-199,7
+201,7
@@
reg_t sim_t::get_reg(const std::vector<std::string>& args)
return p->state.XPR[r];
}
return p->state.XPR[r];
}
-reg_t sim_t::get_freg(const std::vector<std::string>& args)
+
f
reg_t sim_t::get_freg(const std::vector<std::string>& args)
{
if(args.size() != 2)
throw trap_interactive();
{
if(args.size() != 2)
throw trap_interactive();
@@
-231,23
+233,29
@@
void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::strin
union fpr
{
union fpr
{
- reg_t r;
+
f
reg_t r;
float s;
double d;
};
float s;
double d;
};
+void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::string>& args)
+{
+ freg_t r = get_freg(args);
+ fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64 "\n", r.v[1], r.v[0]);
+}
+
void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
{
fpr f;
f.r = get_freg(args);
void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
{
fpr f;
f.r = get_freg(args);
- fprintf(stderr, "%g\n",
f.s
);
+ fprintf(stderr, "%g\n",
isBoxedF32(f.r) ? (double)f.s : NAN
);
}
void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args)
{
fpr f;
f.r = get_freg(args);
}
void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args)
{
fpr f;
f.r = get_freg(args);
- fprintf(stderr, "%g\n",
f.d
);
+ fprintf(stderr, "%g\n",
isBoxedF64(f.r) ? f.d : NAN
);
}
reg_t sim_t::get_mem(const std::vector<std::string>& args)
}
reg_t sim_t::get_mem(const std::vector<std::string>& args)