projects
/
riscv-isa-sim.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Include math.h for NAN (#137)
[riscv-isa-sim.git]
/
riscv
/
interactive.cc
diff --git
a/riscv/interactive.cc
b/riscv/interactive.cc
index 6ae1892f001ea2c2ff9878a468eeb0c666727b88..dbcd22455d5fe6fdb75388946df176d7227ca6df 100644
(file)
--- a/
riscv/interactive.cc
+++ b/
riscv/interactive.cc
@@
-3,7
+3,7
@@
#include "decode.h"
#include "disasm.h"
#include "sim.h"
#include "decode.h"
#include "disasm.h"
#include "sim.h"
-#include "
htif
.h"
+#include "
mmu
.h"
#include <sys/mman.h>
#include <termios.h>
#include <map>
#include <sys/mman.h>
#include <termios.h>
#include <map>
@@
-17,13
+17,16
@@
#include <string>
#include <vector>
#include <algorithm>
#include <string>
#include <vector>
#include <algorithm>
+#include <math.h>
+
+DECLARE_TRAP(-1, interactive)
processor_t *sim_t::get_core(const std::string& i)
{
char *ptr;
unsigned long p = strtoul(i.c_str(), &ptr, 10);
processor_t *sim_t::get_core(const std::string& i)
{
char *ptr;
unsigned long p = strtoul(i.c_str(), &ptr, 10);
- if (*ptr || p >=
num_cores
())
- throw trap_i
llegal_instruction
();
+ if (*ptr || p >=
procs.size
())
+ throw trap_i
nteractive
();
return get_core(p);
}
return get_core(p);
}
@@
-64,6
+67,7
@@
void sim_t::interactive()
funcs["r"] = funcs["run"];
funcs["rs"] = &sim_t::interactive_run_silent;
funcs["reg"] = &sim_t::interactive_reg;
funcs["r"] = funcs["run"];
funcs["rs"] = &sim_t::interactive_run_silent;
funcs["reg"] = &sim_t::interactive_reg;
+ funcs["freg"] = &sim_t::interactive_freg;
funcs["fregs"] = &sim_t::interactive_fregs;
funcs["fregd"] = &sim_t::interactive_fregd;
funcs["pc"] = &sim_t::interactive_pc;
funcs["fregs"] = &sim_t::interactive_fregs;
funcs["fregd"] = &sim_t::interactive_fregd;
funcs["pc"] = &sim_t::interactive_pc;
@@
-76,7
+80,7
@@
void sim_t::interactive()
funcs["help"] = &sim_t::interactive_help;
funcs["h"] = funcs["help"];
funcs["help"] = &sim_t::interactive_help;
funcs["h"] = funcs["help"];
- while (!
htif->
done())
+ while (!done())
{
std::cerr << ": " << std::flush;
std::string s = readline(2);
{
std::cerr << ": " << std::flush;
std::string s = readline(2);
@@
-99,6
+103,8
@@
void sim_t::interactive()
{
if(funcs.count(cmd))
(this->*funcs[cmd])(cmd, args);
{
if(funcs.count(cmd))
(this->*funcs[cmd])(cmd, args);
+ else
+ fprintf(stderr, "Unknown command %s\n", cmd.c_str());
}
catch(trap_t t) {}
}
}
catch(trap_t t) {}
}
@@
-147,7
+153,7
@@
void sim_t::interactive_run(const std::string& cmd, const std::vector<std::strin
size_t steps = args.size() ? atoll(args[0].c_str()) : -1;
ctrlc_pressed = false;
set_procs_debug(noisy);
size_t steps = args.size() ? atoll(args[0].c_str()) : -1;
ctrlc_pressed = false;
set_procs_debug(noisy);
- for (size_t i = 0; i < steps && !ctrlc_pressed && !
htif->
done(); i++)
+ for (size_t i = 0; i < steps && !ctrlc_pressed && !done(); i++)
step(1);
}
step(1);
}
@@
-159,7
+165,7
@@
void sim_t::interactive_quit(const std::string& cmd, const std::vector<std::stri
reg_t sim_t::get_pc(const std::vector<std::string>& args)
{
if(args.size() != 1)
reg_t sim_t::get_pc(const std::vector<std::string>& args)
{
if(args.size() != 1)
- throw trap_i
llegal_instruction
();
+ throw trap_i
nteractive
();
processor_t *p = get_core(args[0]);
return p->state.pc;
processor_t *p = get_core(args[0]);
return p->state.pc;
@@
-173,7
+179,7
@@
void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string
reg_t sim_t::get_reg(const std::vector<std::string>& args)
{
if(args.size() != 2)
reg_t sim_t::get_reg(const std::vector<std::string>& args)
{
if(args.size() != 2)
- throw trap_i
llegal_instruction
();
+ throw trap_i
nteractive
();
processor_t *p = get_core(args[0]);
processor_t *p = get_core(args[0]);
@@
-183,30
+189,29
@@
reg_t sim_t::get_reg(const std::vector<std::string>& args)
r = strtoul(args[1].c_str(), &ptr, 10);
if (*ptr) {
#define DECLARE_CSR(name, number) if (args[1] == #name) return p->get_csr(number);
r = strtoul(args[1].c_str(), &ptr, 10);
if (*ptr) {
#define DECLARE_CSR(name, number) if (args[1] == #name) return p->get_csr(number);
- if (0) ;
- #include "encoding.h"
- else r = NXPR;
+ #include "encoding.h" // generates if's for all csrs
+ r = NXPR; // else case (csr name not found)
#undef DECLARE_CSR
}
}
if (r >= NXPR)
#undef DECLARE_CSR
}
}
if (r >= NXPR)
- throw trap_i
llegal_instruction
();
+ throw trap_i
nteractive
();
return p->state.XPR[r];
}
return p->state.XPR[r];
}
-reg_t sim_t::get_freg(const std::vector<std::string>& args)
+
f
reg_t sim_t::get_freg(const std::vector<std::string>& args)
{
if(args.size() != 2)
{
if(args.size() != 2)
- throw trap_i
llegal_instruction
();
+ throw trap_i
nteractive
();
processor_t *p = get_core(args[0]);
int r = std::find(fpr_name, fpr_name + NFPR, args[1]) - fpr_name;
if (r == NFPR)
r = atoi(args[1].c_str());
if (r >= NFPR)
processor_t *p = get_core(args[0]);
int r = std::find(fpr_name, fpr_name + NFPR, args[1]) - fpr_name;
if (r == NFPR)
r = atoi(args[1].c_str());
if (r >= NFPR)
- throw trap_i
llegal_instruction
();
+ throw trap_i
nteractive
();
return p->state.FPR[r];
}
return p->state.FPR[r];
}
@@
-217,7
+222,7
@@
void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::strin
// Show all the regs!
processor_t *p = get_core(args[0]);
// Show all the regs!
processor_t *p = get_core(args[0]);
- for (int r = 0; r < N
F
PR; ++r) {
+ for (int r = 0; r < N
X
PR; ++r) {
fprintf(stderr, "%-4s: 0x%016" PRIx64 " ", xpr_name[r], p->state.XPR[r]);
if ((r + 1) % 4 == 0)
fprintf(stderr, "\n");
fprintf(stderr, "%-4s: 0x%016" PRIx64 " ", xpr_name[r], p->state.XPR[r]);
if ((r + 1) % 4 == 0)
fprintf(stderr, "\n");
@@
-228,29
+233,35
@@
void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::strin
union fpr
{
union fpr
{
- reg_t r;
+
f
reg_t r;
float s;
double d;
};
float s;
double d;
};
+void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::string>& args)
+{
+ freg_t r = get_freg(args);
+ fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64 "\n", r.v[1], r.v[0]);
+}
+
void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
{
fpr f;
f.r = get_freg(args);
void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
{
fpr f;
f.r = get_freg(args);
- fprintf(stderr, "%g\n",
f.s
);
+ fprintf(stderr, "%g\n",
isBoxedF32(f.r) ? (double)f.s : NAN
);
}
void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args)
{
fpr f;
f.r = get_freg(args);
}
void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args)
{
fpr f;
f.r = get_freg(args);
- fprintf(stderr, "%g\n",
f.d
);
+ fprintf(stderr, "%g\n",
isBoxedF64(f.r) ? f.d : NAN
);
}
reg_t sim_t::get_mem(const std::vector<std::string>& args)
{
if(args.size() != 1 && args.size() != 2)
}
reg_t sim_t::get_mem(const std::vector<std::string>& args)
{
if(args.size() != 1 && args.size() != 2)
- throw trap_i
llegal_instruction
();
+ throw trap_i
nteractive
();
std::string addr_str = args[0];
mmu_t* mmu = debug_mmu;
std::string addr_str = args[0];
mmu_t* mmu = debug_mmu;
@@
-292,7
+303,7
@@
void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::strin
void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args)
{
if(args.size() != 1)
void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args)
{
if(args.size() != 1)
- throw trap_i
llegal_instruction
();
+ throw trap_i
nteractive
();
reg_t addr = strtol(args[0].c_str(),NULL,16);
reg_t addr = strtol(args[0].c_str(),NULL,16);